ddr2_eval.lpf

DDR2 的控制器

 FREQUENCY PORT "clk_in" 220 MHz;
 FREQUENCY NET "k_clk_c" 220 MHz;
 USE PRIMARY NET "k_clk_c" ;
 BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 BLOCK PATH FROM PORT "rst_n";
 IOBUF ALLPORTS IO_TYPE=SSTL18_II;
 DEFINE PORT GROUP "EM_DDR_DIFFERENTIAL_GRP" "em_ddr_clk*" "em_ddr_dqs*";
 IOBUF GROUP "EM_DDR_DIFFERENTIAL_GRP" IO_TYPE=SSTL18D_II;

 INPUT_SETUP PORT "*cmd*" 5.00 ns HOLD 1.000000 ns CLKPORT "clk_in" ;
 INPUT_SETUP PORT "*addr*" 5.00 ns HOLD 1.000000 ns CLKPORT "clk_in" ;
 INPUT_SETUP PORT "*init_start*" 5.00 ns HOLD 1.000000 ns CLKPORT "clk_in" ;
 INPUT_SETUP PORT "*write_data*" 5.00 ns HOLD 1.000000 ns CLKPORT "clk_in" ;
 INPUT_SETUP PORT "*data_mask*" 5.00 ns HOLD 1.000000 ns CLKPORT "clk_in" ;
 CLOCK_TO_OUT PORT "read_data*" 5.00 ns CLKPORT "clk_in" ;
 CLOCK_TO_OUT PORT "cmd_rdy*" 5.00 ns CLKPORT "clk_in" ;
 CLOCK_TO_OUT PORT "data_rdy*" 5.00 ns CLKPORT "clk_in" ;
 CLOCK_TO_OUT PORT "init_done*" 5.00 ns CLKPORT "clk_in" ;

MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/U1_cdl/*pstd_cas*" 2 x; 
MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/U1_cdl/*cas_latency*" 2 x;
MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/*latency*" 2 x;
MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/*twr_wl_bl*" 2 x;
MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/*twr_plus_trp*" 2 x;
MULTICYCLE TO CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/*twr_wl_bl*" 2 x;
MULTICYCLE TO CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/*twr_plus_trp*" 2 x;
MULTICYCLE FROM CELL "*U1_LSC_IP_ddr2/*dv_mod/delay_cnt*" TO CELL "*U1_LSC_IP_ddr2/*dv_mod/dqs_pio_read_e*" 2 x;

MAXDELAY NET "*U1_ddr_sdram_mem_core/U1_LSC_IP_ddr2/*dv_mod/u1_pio_read_macro/pio_read_pos*" 0.300 ns;

BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/trc_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/trrd_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/twtr_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/trtp_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/tras_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/trcd_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/trp_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/twr_reg*"  ;
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cdl/ar_burst_cnt*";
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/bl_cycle*";
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cal/U1_cal_ddr2_csm/bl_cnt_*";
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cdl/burst_len*";
BLOCK PATH FROM CELL "*U1_LSC_IP_ddr2/U1_cdl/burst_*";