ddr_sdram_mem_top.srs

DDR2 的控制器

@E
@ 
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7.5, Build 161R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Oct 12 14:50:05 2007
#
#
#OPTIONS:"|-top|ddr_sdram_mem_top|-infer_seqShift|-fixsmult|-nram|-divnmod|-autosm|-I|d:\\DDR2_S~1\\DDR_P_~1\\ddr2\\impl\\|-I|E:\\ISPTOOLS7_0\\SYNPBASE\\lib|-v2001|-devicelib|E:\\ISPTOOLS7_0\\SYNPBASE\\lib\\lucent\\ecp2m.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-ram|-ll|2000"
#CUR:"E:\\ISPTOOLS7_0\\SYNPBASE\\bin\\c_ver.exe":1176797944
#CUR:"E:\\ISPTOOLS7_0\\SYNPBASE\\lib\\lucent\\ecp2m.v":1176962836
#CUR:"e:\\ispTOOLS7_0\\ispcpld\\..\\cae_library\\synthesis\\verilog\\ecp2m.v":1180574804
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\ddr2\\impl\\ddr2_eval.h":1192168626
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\models\\ecp2m\\pll_266M.v":1192171468
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\models\\ecp2m\\ddr_dqs_io.v":1167011182
#CUR:"ddr_sdram_mem_params.v":1192168790
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\models\\ecp2m\\ddr_dm_io.v":1167011172
#CUR:"ddr_sdram_mem_params.v":1192168790
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\models\\ecp2m\\ddr_data_io.v":1167011166
#CUR:"ddr_sdram_mem_params.v":1192168790
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\models\\ecp2m\\ddr_sdram_mem_io_top.v":1176346690
#CUR:"ddr_sdram_mem_params.v":1192168790
#CUR:"D:\\DDR2_S~1\\ddr2_bb.v":1192168512
#CUR:"ddr_sdram_mem_params.v":1192168790
#CUR:"D:\\DDR2_S~1\\DDR_P_~1\\ddr2\\src\\rtl\\top\\ecp2m\\ddr_sdram_mem_top.v":1192171784
#CUR:"ddr_sdram_mem_params.v":1192168790
f "E:\ISPTOOLS7_0\SYNPBASE\lib\lucent\ecp2m.v"; # file 0
af .is_verilog 1;
f "e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v"; # file 1
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\ddr2\impl\ddr2_eval.h"; # file 2
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\models\ecp2m\pll_266M.v"; # file 3
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dqs_io.v"; # file 4
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 5
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dm_io.v"; # file 6
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 7
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_data_io.v"; # file 8
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 9
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v"; # file 10
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 11
af .is_verilog 1;
f "D:\DDR2_S~1\ddr2_bb.v"; # file 12
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 13
af .is_verilog 1;
f "D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v"; # file 14
af .is_verilog 1;
f ".\ddr_sdram_mem_params.v"; # file 15
af .is_verilog 1;
@E
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---------------------------------@-
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