ddr_sdram_mem_top.vhm

DDR2 的控制器

      em_ddr_dqs : inout std_logic_vector(0 downto 0);
      ddr_dqs_en_d0 :  in std_logic;
      dqsdel_0 :  in std_logic;
      k_clk_c :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_dqs_1
    port(
      ddr_dqs_out_d0 : in std_logic_vector(7 downto 6);
      data_valid : out std_logic_vector(3 downto 3);
      dqsxfer_clk : out std_logic_vector(3 downto 3);
      ddrclkpol : out std_logic_vector(3 downto 3);
      dqsin_clk : out std_logic_vector(3 downto 3);
      dqs_pio_read : in std_logic_vector(3 downto 3);
      em_ddr_dqs : inout std_logic_vector(3 downto 3);
      ddr_dqs_en_d0 :  in std_logic;
      dqsdel_0 :  in std_logic;
      k_clk_c :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_dqs_2
    port(
      ddr_dqs_out_d0 : in std_logic_vector(5 downto 4);
      data_valid : out std_logic_vector(2 downto 2);
      dqsxfer_clk : out std_logic_vector(2 downto 2);
      ddrclkpol : out std_logic_vector(2 downto 2);
      dqsin_clk : out std_logic_vector(2 downto 2);
      dqs_pio_read : in std_logic_vector(2 downto 2);
      em_ddr_dqs : inout std_logic_vector(2 downto 2);
      ddr_dqs_en_d0 :  in std_logic;
      dqsdel_0 :  in std_logic;
      k_clk_c :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_dqs_3
    port(
      ddr_dqs_out_d0 : in std_logic_vector(3 downto 2);
      data_valid : out std_logic_vector(1 downto 1);
      dqsxfer_clk : out std_logic_vector(1 downto 1);
      ddrclkpol : out std_logic_vector(1 downto 1);
      dqsin_clk : out std_logic_vector(1 downto 1);
      dqs_pio_read : in std_logic_vector(1 downto 1);
      em_ddr_dqs : inout std_logic_vector(1 downto 1);
      ddr_dqs_en_d0 :  in std_logic;
      dqsdel_0 :  in std_logic;
      k_clk_c :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
begin
  \U[0].BIDI_DQS\: bidi_dqs port map (
      ddr_dqs_out_d0(0) => ddr_dqs_out_d0(0),
      ddr_dqs_out_d0(1) => ddr_dqs_out_d0(1),
      data_valid(0) => data_valid(0),
      dqsxfer_clk(0) => dqsxfer_clk(0),
      ddrclkpol(0) => ddrclkpol(0),
      dqsin_clk(0) => dqsin_clk(0),
      dqs_pio_read(0) => dqs_pio_read(0),
      em_ddr_dqs(0) => em_ddr_dqs(0),
      ddr_dqs_en_d0 => ddr_dqs_en_d0,
      dqsdel_0 => dqsdel_0,
      k_clk_c => k_clk_c,
      rst_acth => rst_acth);
  \U[3].BIDI_DQS\: bidi_dqs_1 port map (
      ddr_dqs_out_d0(6) => ddr_dqs_out_d0(6),
      ddr_dqs_out_d0(7) => ddr_dqs_out_d0(7),
      data_valid(3) => data_valid(3),
      dqsxfer_clk(3) => dqsxfer_clk(3),
      ddrclkpol(3) => ddrclkpol(3),
      dqsin_clk(3) => dqsin_clk(3),
      dqs_pio_read(3) => dqs_pio_read(3),
      em_ddr_dqs(3) => em_ddr_dqs(3),
      ddr_dqs_en_d0 => ddr_dqs_en_d0,
      dqsdel_0 => dqsdel_0,
      k_clk_c => k_clk_c,
      rst_acth => rst_acth);
  \U[2].BIDI_DQS\: bidi_dqs_2 port map (
      ddr_dqs_out_d0(4) => ddr_dqs_out_d0(4),
      ddr_dqs_out_d0(5) => ddr_dqs_out_d0(5),
      data_valid(2) => data_valid(2),
      dqsxfer_clk(2) => dqsxfer_clk(2),
      ddrclkpol(2) => ddrclkpol(2),
      dqsin_clk(2) => dqsin_clk(2),
      dqs_pio_read(2) => dqs_pio_read(2),
      em_ddr_dqs(2) => em_ddr_dqs(2),
      ddr_dqs_en_d0 => ddr_dqs_en_d0,
      dqsdel_0 => dqsdel_0,
      k_clk_c => k_clk_c,
      rst_acth => rst_acth);
  \U[1].BIDI_DQS\: bidi_dqs_3 port map (
      ddr_dqs_out_d0(2) => ddr_dqs_out_d0(2),
      ddr_dqs_out_d0(3) => ddr_dqs_out_d0(3),
      data_valid(1) => data_valid(1),
      dqsxfer_clk(1) => dqsxfer_clk(1),
      ddrclkpol(1) => ddrclkpol(1),
      dqsin_clk(1) => dqsin_clk(1),
      dqs_pio_read(1) => dqs_pio_read(1),
      em_ddr_dqs(1) => em_ddr_dqs(1),
      ddr_dqs_en_d0 => ddr_dqs_en_d0,
      dqsdel_0 => dqsdel_0,
      k_clk_c => k_clk_c,
      rst_acth => rst_acth);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity ddr_dm_io is
port(
  em_ddr_dm_c : out std_logic_vector(1 downto 0);
  dqsxfer_clk : in std_logic_vector(1 downto 0);
  ddr_dm_d1 : in std_logic_vector(3 downto 0);
  k_clk_c :  in std_logic;
  rst_acth :  in std_logic);
end ddr_dm_io;

architecture beh of ddr_dm_io is
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
begin
  RST <= rst_acth;
  \U[1].ODDRB\: ODDRMXA port map (
      DA => ddr_dm_d1(1),
      DB => ddr_dm_d1(3),
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(1),
      Q => em_ddr_dm_c(1));
  \U[0].ODDRB\: ODDRMXA port map (
      DA => ddr_dm_d1(0),
      DB => ddr_dm_d1(2),
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(0),
      Q => em_ddr_dm_c(0));
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity ddr_data_io is
port(
  em_ddr_data : inout std_logic_vector(15 downto 0);
  dqsxfer_clk : in std_logic_vector(3 downto 0);
  ddr_write_data_d1 : in std_logic_vector(31 downto 0);
  dqsin_clk : in std_logic_vector(3 downto 0);
  ddrclkpol : in std_logic_vector(3 downto 0);
  ddr_read_data : out std_logic_vector(31 downto 0);
  rst_acth :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  k_clk_c :  in std_logic;
  VCC :  in std_logic);
end ddr_data_io;

architecture beh of ddr_data_io is
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component bidi_cell
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(1 downto 1);
      dqsin_clk : in std_logic_vector(1 downto 1);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(1 downto 1);
      em_ddr_data : inout std_logic_vector(4 downto 4);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_1
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(2 downto 2);
      dqsin_clk : in std_logic_vector(2 downto 2);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(2 downto 2);
      em_ddr_data : inout std_logic_vector(10 downto 10);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_2
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(1 downto 1);
      dqsin_clk : in std_logic_vector(1 downto 1);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(1 downto 1);
      em_ddr_data : inout std_logic_vector(7 downto 7);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_3
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(0 downto 0);
      dqsin_clk : in std_logic_vector(0 downto 0);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(0 downto 0);
      em_ddr_data : inout std_logic_vector(3 downto 3);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_4
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(3 downto 3);
      dqsin_clk : in std_logic_vector(3 downto 3);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(3 downto 3);
      em_ddr_data : inout std_logic_vector(13 downto 13);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_5
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(2 downto 2);
      dqsin_clk : in std_logic_vector(2 downto 2);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(2 downto 2);
      em_ddr_data : inout std_logic_vector(11 downto 11);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_6
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(2 downto 2);
      dqsin_clk : in std_logic_vector(2 downto 2);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(2 downto 2);
      em_ddr_data : inout std_logic_vector(8 downto 8);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_7
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(1 downto 1);
      dqsin_clk : in std_logic_vector(1 downto 1);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(1 downto 1);
      em_ddr_data : inout std_logic_vector(5 downto 5);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_8
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(0 downto 0);
      dqsin_clk : in std_logic_vector(0 downto 0);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(0 downto 0);
      em_ddr_data : inout std_logic_vector(2 downto 2);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_9
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(3 downto 3);
      dqsin_clk : in std_logic_vector(3 downto 3);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(3 downto 3);
      em_ddr_data : inout std_logic_vector(12 downto 12);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_10
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(2 downto 2);
      dqsin_clk : in std_logic_vector(2 downto 2);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(2 downto 2);
      em_ddr_data : inout std_logic_vector(9 downto 9);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_11
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(1 downto 1);
      dqsin_clk : in std_logic_vector(1 downto 1);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(1 downto 1);
      em_ddr_data : inout std_logic_vector(6 downto 6);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_12
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(0 downto 0);
      dqsin_clk : in std_logic_vector(0 downto 0);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(0 downto 0);
      em_ddr_data : inout std_logic_vector(1 downto 1);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_13
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(0 downto 0);
      dqsin_clk : in std_logic_vector(0 downto 0);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(0 downto 0);
      em_ddr_data : inout std_logic_vector(0 downto 0);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_14
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(3 downto 3);
      dqsin_clk : in std_logic_vector(3 downto 3);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(3 downto 3);
      em_ddr_data : inout std_logic_vector(14 downto 14);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
  component bidi_cell_15
    port(
      ddr_read_data_16 :  out std_logic;
      ddr_read_data_0 :  out std_logic;
      ddrclkpol : in std_logic_vector(3 downto 3);
      dqsin_clk : in std_logic_vector(3 downto 3);
      ddr_write_data_d1_16 :  in std_logic;
      ddr_write_data_d1_0 :  in std_logic;
      dqsxfer_clk : in std_logic_vector(3 downto 3);
      em_ddr_data : inout std_logic_vector(15 downto 15);
      VCC :  in std_logic;
      k_clk_c :  in std_logic;
      ddr_write_data_valid_d0 :  in std_logic;
      rst_acth :  in std_logic  );
  end component;
begin
  \U[4].BIDI_CELL\: bidi_cell port map (
      ddr_read_data_16 => ddr_read_data(20),
      ddr_read_data_0 => ddr_read_data(4),
      ddrclkpol(1) => ddrclkpol(1),
      dqsin_clk(1) => dqsin_clk(1),
      ddr_write_data_d1_16 => ddr_write_data_d1(20),
      ddr_write_data_d1_0 => ddr_write_data_d1(4),
      dqsxfer_clk(1) => dqsxfer_clk(1),
      em_ddr_data(4) => em_ddr_data(4),
      VCC => VCC,
      k_clk_c => k_clk_c,
      ddr_write_data_valid_d0 => ddr_write_data_valid_d0,
      rst_acth => rst_acth);
  \U[10].BIDI_CELL\: bidi_cell_1 port map (
      ddr_read_data_16 => ddr_read_data(26),
      ddr_read_data_0 => ddr_read_data(10),
      ddrclkpol(2) => ddrclkpol(2),
      dqsin_clk(2) => dqsin_clk(2),
      ddr_write_data_d1_16 => ddr_write_data_d1(26),
      ddr_write_data_d1_0 => ddr_write_data_d1(10),
      dqsxfer_clk(2) => dqsxfer_clk(2),
      em_ddr_data(10) => em_ddr_data(10),
      VCC => VCC,
      k_clk_c => k_clk_c,
      ddr_write_data_valid_d0 => ddr_write_data_valid_d0,
      rst_acth => rst_acth);
  \U[7].BIDI_CELL\: bidi_cell_2 port map (
      ddr_read_data_16 => ddr_read_data(23),
      ddr_read_data_0 => ddr_read_data(7),
      ddrclkpol(1) => ddrclkpol(1),
      dqsi