ddr_sdram_mem_top.vhm

DDR2 的控制器

library ecp2;
use ecp2.components.all;

entity bidi_cell_9 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(3 downto 3);
  dqsin_clk : in std_logic_vector(3 downto 3);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(3 downto 3);
  em_ddr_data : inout std_logic_vector(12 downto 12);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_9;

architecture beh of bidi_cell_9 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(12),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(3),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(3),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(3),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,
      RST => RST,
      CE => VCC,
      DDRCLKPOL => ddrclkpol(3),
      QA => ddr_read_data_0,
      QB => ddr_read_data_16);
  GND <= '0';
  NN_1 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_8 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(0 downto 0);
  dqsin_clk : in std_logic_vector(0 downto 0);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(0 downto 0);
  em_ddr_data : inout std_logic_vector(2 downto 2);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_8;

architecture beh of bidi_cell_8 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(2),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(0),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(0),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(0),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,
      RST => RST,
      CE => VCC,
      DDRCLKPOL => ddrclkpol(0),
      QA => ddr_read_data_0,
      QB => ddr_read_data_16);
  GND <= '0';
  NN_1 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_7 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(1 downto 1);
  dqsin_clk : in std_logic_vector(1 downto 1);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(1 downto 1);
  em_ddr_data : inout std_logic_vector(5 downto 5);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_7;

architecture beh of bidi_cell_7 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(5),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(1),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(1),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(1),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,
      RST => RST,
      CE => VCC,
      DDRCLKPOL => ddrclkpol(1),
      QA => ddr_read_data_0,
      QB => ddr_read_data_16);
  GND <= '0';
  NN_1 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_6 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(2 downto 2);
  dqsin_clk : in std_logic_vector(2 downto 2);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(2 downto 2);
  em_ddr_data : inout std_logic_vector(8 downto 8);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_6;

architecture beh of bidi_cell_6 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(8),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(2),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(2),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(2),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,
      RST => RST,
      CE => VCC,
      DDRCLKPOL => ddrclkpol(2),
      QA => ddr_read_data_0,
      QB => ddr_read_data_16);
  GND <= '0';
  NN_1 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_5 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(2 downto 2);
  dqsin_clk : in std_logic_vector(2 downto 2);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(2 downto 2);
  em_ddr_data : inout std_logic_vector(11 downto 11);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_5;

architecture beh of bidi_cell_5 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(11),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(2),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(2),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(2),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,
      RST => RST,
      CE => VCC,
      DDRCLKPOL => ddrclkpol(2),
      QA => ddr_read_data_0,
      QB => ddr_read_data_16);
  GND <= '0';
  NN_1 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_4 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(3 downto 3);
  dqsin_clk : in std_logic_vector(3 downto 3);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(3 downto 3);
  em_ddr_data : inout std_logic_vector(13 downto 13);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;