ddr_sdram_mem_top.vhm

DDR2 的控制器

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Fri Oct 12 14:50:07 2007
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Fri Oct 12 14:50:07 2007
--

-- No definition of black box work.DQSBUFC.verilog
-- No definition of black box work.IDDRMFX1A.verilog
-- No definition of black box work.ODDRMXA.verilog
-- No definition of black box work.ODDRXC.verilog
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_dqs_3 is
port(
  ddr_dqs_out_d0 : in std_logic_vector(3 downto 2);
  data_valid : out std_logic_vector(1 downto 1);
  dqsxfer_clk : out std_logic_vector(1 downto 1);
  ddrclkpol : out std_logic_vector(1 downto 1);
  dqsin_clk : out std_logic_vector(1 downto 1);
  dqs_pio_read : in std_logic_vector(1 downto 1);
  em_ddr_dqs : inout std_logic_vector(1 downto 1);
  ddr_dqs_en_d0 :  in std_logic;
  dqsdel_0 :  in std_logic;
  k_clk_c :  in std_logic;
  rst_acth :  in std_logic);
end bidi_dqs_3;

architecture beh of bidi_dqs_3 is
  signal DQSI : std_logic_vector(1 to 1);
  signal PRMBDET : std_logic_vector(1 to 1);
  signal OUT_TO_BB : std_logic ;
  signal TRI_EN_REG : std_logic ;
  signal RST : std_logic ;
  signal DQSC_1 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DQSBUFC
    port(
      DQSI :  in std_logic;
      CLK :  in std_logic;
      XCLK :  in std_logic;
      READ :  in std_logic;
      DQSDEL :  in std_logic;
      DQSO :  out std_logic;
      DDRCLKPOL :  out std_logic;
      DQSC :  out std_logic;
      PRMBDET :  out std_logic;
      DQSXFER :  out std_logic;
      DATAVALID :  out std_logic  );
  end component;
  component ODDRXC
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      Q :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_dqs(1),
      I => OUT_TO_BB,
      T => TRI_EN_REG,
      O => DQSI(1));
  RST <= rst_acth;
  U1_DQSBUFC: DQSBUFC port map (
      DQSI => DQSI(1),
      CLK => k_clk_c,
      XCLK => k_clk_c,
      READ => dqs_pio_read(1),
      DQSDEL => dqsdel_0,
      DQSO => dqsin_clk(1),
      DDRCLKPOL => ddrclkpol(1),
      DQSC => DQSC_1,
      PRMBDET => PRMBDET(1),
      DQSXFER => dqsxfer_clk(1),
      DATAVALID => data_valid(1));
  U1_TODDRXC: ODDRXC port map (
      DA => ddr_dqs_en_d0,
      DB => ddr_dqs_en_d0,
      CLK => k_clk_c,
      RST => RST,
      Q => TRI_EN_REG);
  U1_ODDRXC: ODDRXC port map (
      DA => ddr_dqs_out_d0(3),
      DB => ddr_dqs_out_d0(2),
      CLK => k_clk_c,
      RST => RST,
      Q => OUT_TO_BB);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_dqs_2 is
port(
  ddr_dqs_out_d0 : in std_logic_vector(5 downto 4);
  data_valid : out std_logic_vector(2 downto 2);
  dqsxfer_clk : out std_logic_vector(2 downto 2);
  ddrclkpol : out std_logic_vector(2 downto 2);
  dqsin_clk : out std_logic_vector(2 downto 2);
  dqs_pio_read : in std_logic_vector(2 downto 2);
  em_ddr_dqs : inout std_logic_vector(2 downto 2);
  ddr_dqs_en_d0 :  in std_logic;
  dqsdel_0 :  in std_logic;
  k_clk_c :  in std_logic;
  rst_acth :  in std_logic);
end bidi_dqs_2;

architecture beh of bidi_dqs_2 is
  signal DQSI : std_logic_vector(2 to 2);
  signal PRMBDET : std_logic_vector(2 to 2);
  signal OUT_TO_BB : std_logic ;
  signal TRI_EN_REG : std_logic ;
  signal RST : std_logic ;
  signal DQSC_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DQSBUFC
    port(
      DQSI :  in std_logic;
      CLK :  in std_logic;
      XCLK :  in std_logic;
      READ :  in std_logic;
      DQSDEL :  in std_logic;
      DQSO :  out std_logic;
      DDRCLKPOL :  out std_logic;
      DQSC :  out std_logic;
      PRMBDET :  out std_logic;
      DQSXFER :  out std_logic;
      DATAVALID :  out std_logic  );
  end component;
  component ODDRXC
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      Q :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_dqs(2),
      I => OUT_TO_BB,
      T => TRI_EN_REG,
      O => DQSI(2));
  RST <= rst_acth;
  U1_DQSBUFC: DQSBUFC port map (
      DQSI => DQSI(2),
      CLK => k_clk_c,
      XCLK => k_clk_c,
      READ => dqs_pio_read(2),
      DQSDEL => dqsdel_0,
      DQSO => dqsin_clk(2),
      DDRCLKPOL => ddrclkpol(2),
      DQSC => DQSC_0,
      PRMBDET => PRMBDET(2),
      DQSXFER => dqsxfer_clk(2),
      DATAVALID => data_valid(2));
  U1_TODDRXC: ODDRXC port map (
      DA => ddr_dqs_en_d0,
      DB => ddr_dqs_en_d0,
      CLK => k_clk_c,
      RST => RST,
      Q => TRI_EN_REG);
  U1_ODDRXC: ODDRXC port map (
      DA => ddr_dqs_out_d0(5),
      DB => ddr_dqs_out_d0(4),
      CLK => k_clk_c,
      RST => RST,
      Q => OUT_TO_BB);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_dqs_1 is
port(
  ddr_dqs_out_d0 : in std_logic_vector(7 downto 6);
  data_valid : out std_logic_vector(3 downto 3);
  dqsxfer_clk : out std_logic_vector(3 downto 3);
  ddrclkpol : out std_logic_vector(3 downto 3);
  dqsin_clk : out std_logic_vector(3 downto 3);
  dqs_pio_read : in std_logic_vector(3 downto 3);
  em_ddr_dqs : inout std_logic_vector(3 downto 3);
  ddr_dqs_en_d0 :  in std_logic;
  dqsdel_0 :  in std_logic;
  k_clk_c :  in std_logic;
  rst_acth :  in std_logic);
end bidi_dqs_1;

architecture beh of bidi_dqs_1 is
  signal DQSI : std_logic_vector(3 to 3);
  signal PRMBDET : std_logic_vector(3 to 3);
  signal OUT_TO_BB : std_logic ;
  signal TRI_EN_REG : std_logic ;
  signal RST : std_logic ;
  signal DQSC : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DQSBUFC
    port(
      DQSI :  in std_logic;
      CLK :  in std_logic;
      XCLK :  in std_logic;
      READ :  in std_logic;
      DQSDEL :  in std_logic;
      DQSO :  out std_logic;
      DDRCLKPOL :  out std_logic;
      DQSC :  out std_logic;
      PRMBDET :  out std_logic;
      DQSXFER :  out std_logic;
      DATAVALID :  out std_logic  );
  end component;
  component ODDRXC
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      Q :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_dqs(3),
      I => OUT_TO_BB,
      T => TRI_EN_REG,
      O => DQSI(3));
  RST <= rst_acth;
  U1_DQSBUFC: DQSBUFC port map (
      DQSI => DQSI(3),
      CLK => k_clk_c,
      XCLK => k_clk_c,
      READ => dqs_pio_read(3),
      DQSDEL => dqsdel_0,
      DQSO => dqsin_clk(3),
      DDRCLKPOL => ddrclkpol(3),
      DQSC => DQSC,
      PRMBDET => PRMBDET(3),
      DQSXFER => dqsxfer_clk(3),
      DATAVALID => data_valid(3));
  U1_TODDRXC: ODDRXC port map (
      DA => ddr_dqs_en_d0,
      DB => ddr_dqs_en_d0,
      CLK => k_clk_c,
      RST => RST,
      Q => TRI_EN_REG);
  U1_ODDRXC: ODDRXC port map (
      DA => ddr_dqs_out_d0(7),
      DB => ddr_dqs_out_d0(6),
      CLK => k_clk_c,
      RST => RST,
      Q => OUT_TO_BB);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_dqs is
port(
  ddr_dqs_out_d0 : in std_logic_vector(1 downto 0);
  data_valid : out std_logic_vector(0 downto 0);
  dqsxfer_clk : out std_logic_vector(0 downto 0);
  ddrclkpol : out std_logic_vector(0 downto 0);
  dqsin_clk : out std_logic_vector(0 downto 0);
  dqs_pio_read : in std_logic_vector(0 downto 0);
  em_ddr_dqs : inout std_logic_vector(0 downto 0);
  ddr_dqs_en_d0 :  in std_logic;
  dqsdel_0 :  in std_logic;
  k_clk_c :  in std_logic;
  rst_acth :  in std_logic);
end bidi_dqs;

architecture beh of bidi_dqs is
  signal DQSI : std_logic_vector(0 to 0);
  signal PRMBDET : std_logic_vector(0 to 0);
  signal OUT_TO_BB : std_logic ;
  signal TRI_EN_REG : std_logic ;
  signal RST : std_logic ;
  signal DQSC_2 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DQSBUFC
    port(
      DQSI :  in std_logic;
      CLK :  in std_logic;
      XCLK :  in std_logic;
      READ :  in std_logic;
      DQSDEL :  in std_logic;
      DQSO :  out std_logic;
      DDRCLKPOL :  out std_logic;
      DQSC :  out std_logic;
      PRMBDET :  out std_logic;
      DQSXFER :  out std_logic;
      DATAVALID :  out std_logic  );
  end component;
  component ODDRXC
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      Q :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_dqs(0),
      I => OUT_TO_BB,
      T => TRI_EN_REG,
      O => DQSI(0));
  RST <= rst_acth;
  U1_DQSBUFC: DQSBUFC port map (
      DQSI => DQSI(0),
      CLK => k_clk_c,
      XCLK => k_clk_c,
      READ => dqs_pio_read(0),
      DQSDEL => dqsdel_0,
      DQSO => dqsin_clk(0),
      DDRCLKPOL => ddrclkpol(0),
      DQSC => DQSC_2,
      PRMBDET => PRMBDET(0),
      DQSXFER => dqsxfer_clk(0),
      DATAVALID => data_valid(0));
  U1_TODDRXC: ODDRXC port map (
      DA => ddr_dqs_en_d0,
      DB => ddr_dqs_en_d0,
      CLK => k_clk_c,
      RST => RST,
      Q => TRI_EN_REG);
  U1_ODDRXC: ODDRXC port map (
      DA => ddr_dqs_out_d0(1),
      DB => ddr_dqs_out_d0(0),
      CLK => k_clk_c,
      RST => RST,
      Q => OUT_TO_BB);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity bidi_cell_15 is
port(
  ddr_read_data_16 :  out std_logic;
  ddr_read_data_0 :  out std_logic;
  ddrclkpol : in std_logic_vector(3 downto 3);
  dqsin_clk : in std_logic_vector(3 downto 3);
  ddr_write_data_d1_16 :  in std_logic;
  ddr_write_data_d1_0 :  in std_logic;
  dqsxfer_clk : in std_logic_vector(3 downto 3);
  em_ddr_data : inout std_logic_vector(15 downto 15);
  VCC :  in std_logic;
  k_clk_c :  in std_logic;
  ddr_write_data_valid_d0 :  in std_logic;
  rst_acth :  in std_logic);
end bidi_cell_15;

architecture beh of bidi_cell_15 is
  signal OUT_TO_BB : std_logic ;
  signal OUT_EN_REG : std_logic ;
  signal BB_TO_IN_TMP : std_logic ;
  signal RST : std_logic ;
  signal GND : std_logic ;
  signal NN_1 : std_logic ;
  component ODDRMXA
    port(
      DA :  in std_logic;
      DB :  in std_logic;
      CLK :  in std_logic;
      RST :  in std_logic;
      DQSXFER :  in std_logic;
      Q :  out std_logic  );
  end component;
  component IDDRMFX1A
    port(
      D :  in std_logic;
      ECLK :  in std_logic;
      CLK1 :  in std_logic;
      CLK2 :  in std_logic;
      RST :  in std_logic;
      CE :  in std_logic;
      DDRCLKPOL :  in std_logic;
      QA :  out std_logic;
      QB :  out std_logic  );
  end component;
begin
  U1_BB: BB port map (
      B => em_ddr_data(15),
      I => OUT_TO_BB,
      T => OUT_EN_REG,
      O => BB_TO_IN_TMP);
  RST <= rst_acth;
  U1_TODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_valid_d0,
      DB => ddr_write_data_valid_d0,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(3),
      Q => OUT_EN_REG);
  U1_ODDRMXA: ODDRMXA port map (
      DA => ddr_write_data_d1_0,
      DB => ddr_write_data_d1_16,
      CLK => k_clk_c,
      RST => RST,
      DQSXFER => dqsxfer_clk(3),
      Q => OUT_TO_BB);
  U1_IDDRMFX1A: IDDRMFX1A port map (
      D => BB_TO_IN_TMP,
      ECLK => dqsin_clk(3),
      CLK1 => k_clk_c,
      CLK2 => k_clk_c,