ram_dp.vm

DDR2 的控制器

	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_5_10_DOA0),
	.DOA1(RAM_DP_0_5_10_DOA1),
	.DOA2(RAM_DP_0_5_10_DOA2),
	.DOA3(RAM_DP_0_5_10_DOA3),
	.DOA4(RAM_DP_0_5_10_DOA4),
	.DOA5(RAM_DP_0_5_10_DOA5),
	.DOA6(RAM_DP_0_5_10_DOA6),
	.DOA7(RAM_DP_0_5_10_DOA7),
	.DOA8(RAM_DP_0_5_10_DOA8),
	.DOA9(RAM_DP_0_5_10_DOA9),
	.DOA10(RAM_DP_0_5_10_DOA10),
	.DOA11(RAM_DP_0_5_10_DOA11),
	.DOA12(RAM_DP_0_5_10_DOA12),
	.DOA13(RAM_DP_0_5_10_DOA13),
	.DOA14(RAM_DP_0_5_10_DOA14),
	.DOA15(RAM_DP_0_5_10_DOA15),
	.DOA16(RAM_DP_0_5_10_DOA16),
	.DOA17(RAM_DP_0_5_10_DOA17),
	.DOB0(Q_c[10]),
	.DOB1(Q_c[11]),
	.DOB2(RAM_DP_0_5_10_DOB2),
	.DOB3(RAM_DP_0_5_10_DOB3),
	.DOB4(RAM_DP_0_5_10_DOB4),
	.DOB5(RAM_DP_0_5_10_DOB5),
	.DOB6(RAM_DP_0_5_10_DOB6),
	.DOB7(RAM_DP_0_5_10_DOB7),
	.DOB8(RAM_DP_0_5_10_DOB8),
	.DOB9(RAM_DP_0_5_10_DOB9),
	.DOB10(RAM_DP_0_5_10_DOB10),
	.DOB11(RAM_DP_0_5_10_DOB11),
	.DOB12(RAM_DP_0_5_10_DOB12),
	.DOB13(RAM_DP_0_5_10_DOB13),
	.DOB14(RAM_DP_0_5_10_DOB14),
	.DOB15(RAM_DP_0_5_10_DOB15),
	.DOB16(RAM_DP_0_5_10_DOB16),
	.DOB17(RAM_DP_0_5_10_DOB17)
);
defparam RAM_DP_0_5_10_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_5_10_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_5_10_Z.RESETMODE="SYNC";
defparam RAM_DP_0_5_10_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_5_10_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_5_10_Z.GSR="ENABLED";
// @4:240
  DP16KB RAM_DP_0_4_11_Z (
	.DIA0(GND),
	.DIA1(Data_c[9]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[8]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_4_11_DOA0),
	.DOA1(RAM_DP_0_4_11_DOA1),
	.DOA2(RAM_DP_0_4_11_DOA2),
	.DOA3(RAM_DP_0_4_11_DOA3),
	.DOA4(RAM_DP_0_4_11_DOA4),
	.DOA5(RAM_DP_0_4_11_DOA5),
	.DOA6(RAM_DP_0_4_11_DOA6),
	.DOA7(RAM_DP_0_4_11_DOA7),
	.DOA8(RAM_DP_0_4_11_DOA8),
	.DOA9(RAM_DP_0_4_11_DOA9),
	.DOA10(RAM_DP_0_4_11_DOA10),
	.DOA11(RAM_DP_0_4_11_DOA11),
	.DOA12(RAM_DP_0_4_11_DOA12),
	.DOA13(RAM_DP_0_4_11_DOA13),
	.DOA14(RAM_DP_0_4_11_DOA14),
	.DOA15(RAM_DP_0_4_11_DOA15),
	.DOA16(RAM_DP_0_4_11_DOA16),
	.DOA17(RAM_DP_0_4_11_DOA17),
	.DOB0(Q_c[8]),
	.DOB1(Q_c[9]),
	.DOB2(RAM_DP_0_4_11_DOB2),
	.DOB3(RAM_DP_0_4_11_DOB3),
	.DOB4(RAM_DP_0_4_11_DOB4),
	.DOB5(RAM_DP_0_4_11_DOB5),
	.DOB6(RAM_DP_0_4_11_DOB6),
	.DOB7(RAM_DP_0_4_11_DOB7),
	.DOB8(RAM_DP_0_4_11_DOB8),
	.DOB9(RAM_DP_0_4_11_DOB9),
	.DOB10(RAM_DP_0_4_11_DOB10),
	.DOB11(RAM_DP_0_4_11_DOB11),
	.DOB12(RAM_DP_0_4_11_DOB12),
	.DOB13(RAM_DP_0_4_11_DOB13),
	.DOB14(RAM_DP_0_4_11_DOB14),
	.DOB15(RAM_DP_0_4_11_DOB15),
	.DOB16(RAM_DP_0_4_11_DOB16),
	.DOB17(RAM_DP_0_4_11_DOB17)
);
defparam RAM_DP_0_4_11_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_4_11_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_4_11_Z.RESETMODE="SYNC";
defparam RAM_DP_0_4_11_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_4_11_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_4_11_Z.GSR="ENABLED";
// @4:189
  DP16KB RAM_DP_0_3_12_Z (
	.DIA0(GND),
	.DIA1(Data_c[7]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[6]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_3_12_DOA0),
	.DOA1(RAM_DP_0_3_12_DOA1),
	.DOA2(RAM_DP_0_3_12_DOA2),
	.DOA3(RAM_DP_0_3_12_DOA3),
	.DOA4(RAM_DP_0_3_12_DOA4),
	.DOA5(RAM_DP_0_3_12_DOA5),
	.DOA6(RAM_DP_0_3_12_DOA6),
	.DOA7(RAM_DP_0_3_12_DOA7),
	.DOA8(RAM_DP_0_3_12_DOA8),
	.DOA9(RAM_DP_0_3_12_DOA9),
	.DOA10(RAM_DP_0_3_12_DOA10),
	.DOA11(RAM_DP_0_3_12_DOA11),
	.DOA12(RAM_DP_0_3_12_DOA12),
	.DOA13(RAM_DP_0_3_12_DOA13),
	.DOA14(RAM_DP_0_3_12_DOA14),
	.DOA15(RAM_DP_0_3_12_DOA15),
	.DOA16(RAM_DP_0_3_12_DOA16),
	.DOA17(RAM_DP_0_3_12_DOA17),
	.DOB0(Q_c[6]),
	.DOB1(Q_c[7]),
	.DOB2(RAM_DP_0_3_12_DOB2),
	.DOB3(RAM_DP_0_3_12_DOB3),
	.DOB4(RAM_DP_0_3_12_DOB4),
	.DOB5(RAM_DP_0_3_12_DOB5),
	.DOB6(RAM_DP_0_3_12_DOB6),
	.DOB7(RAM_DP_0_3_12_DOB7),
	.DOB8(RAM_DP_0_3_12_DOB8),
	.DOB9(RAM_DP_0_3_12_DOB9),
	.DOB10(RAM_DP_0_3_12_DOB10),
	.DOB11(RAM_DP_0_3_12_DOB11),
	.DOB12(RAM_DP_0_3_12_DOB12),
	.DOB13(RAM_DP_0_3_12_DOB13),
	.DOB14(RAM_DP_0_3_12_DOB14),
	.DOB15(RAM_DP_0_3_12_DOB15),
	.DOB16(RAM_DP_0_3_12_DOB16),
	.DOB17(RAM_DP_0_3_12_DOB17)
);
defparam RAM_DP_0_3_12_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_3_12_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_3_12_Z.RESETMODE="SYNC";
defparam RAM_DP_0_3_12_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_3_12_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_3_12_Z.GSR="ENABLED";
// @4:138
  DP16KB RAM_DP_0_2_13_Z (
	.DIA0(GND),
	.DIA1(Data_c[5]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[4]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_2_13_DOA0),
	.DOA1(RAM_DP_0_2_13_DOA1),
	.DOA2(RAM_DP_0_2_13_DOA2),
	.DOA3(RAM_DP_0_2_13_DOA3),
	.DOA4(RAM_DP_0_2_13_DOA4),
	.DOA5(RAM_DP_0_2_13_DOA5),
	.DOA6(RAM_DP_0_2_13_DOA6),
	.DOA7(RAM_DP_0_2_13_DOA7),
	.DOA8(RAM_DP_0_2_13_DOA8),
	.DOA9(RAM_DP_0_2_13_DOA9),
	.DOA10(RAM_DP_0_2_13_DOA10),
	.DOA11(RAM_DP_0_2_13_DOA11),
	.DOA12(RAM_DP_0_2_13_DOA12),
	.DOA13(RAM_DP_0_2_13_DOA13),
	.DOA14(RAM_DP_0_2_13_DOA14),
	.DOA15(RAM_DP_0_2_13_DOA15),
	.DOA16(RAM_DP_0_2_13_DOA16),
	.DOA17(RAM_DP_0_2_13_DOA17),
	.DOB0(Q_c[4]),
	.DOB1(Q_c[5]),
	.DOB2(RAM_DP_0_2_13_DOB2),
	.DOB3(RAM_DP_0_2_13_DOB3),
	.DOB4(RAM_DP_0_2_13_DOB4),
	.DOB5(RAM_DP_0_2_13_DOB5),
	.DOB6(RAM_DP_0_2_13_DOB6),
	.DOB7(RAM_DP_0_2_13_DOB7),
	.DOB8(RAM_DP_0_2_13_DOB8),
	.DOB9(RAM_DP_0_2_13_DOB9),
	.DOB10(RAM_DP_0_2_13_DOB10),
	.DOB11(RAM_DP_0_2_13_DOB11),
	.DOB12(RAM_DP_0_2_13_DOB12),
	.DOB13(RAM_DP_0_2_13_DOB13),
	.DOB14(RAM_DP_0_2_13_DOB14),
	.DOB15(RAM_DP_0_2_13_DOB15),
	.DOB16(RAM_DP_0_2_13_DOB16),
	.DOB17(RAM_DP_0_2_13_DOB17)
);
defparam RAM_DP_0_2_13_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_2_13_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_2_13_Z.RESETMODE="SYNC";
defparam RAM_DP_0_2_13_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_2_13_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_2_13_Z.GSR="ENABLED";
// @4:87
  DP16KB RAM_DP_0_1_14_Z (
	.DIA0(GND),
	.DIA1(Data_c[3]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[2]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_1_14_DOA0),
	.DOA1(RAM_DP_0_1_14_DOA1),
	.DOA2(RAM_DP_0_1_14_DOA2),
	.DOA3(RAM_DP_0_1_14_DOA3),
	.DOA4(RAM_DP_0_1_14_DOA4),
	.DOA5(RAM_DP_0_1_14_DOA5),
	.DOA6(RAM_DP_0_1_14_DOA6),
	.DOA7(RAM_DP_0_1_14_DOA7),
	.DOA8(RAM_DP_0_1_14_DOA8),
	.DOA9(RAM_DP_0_1_14_DOA9),
	.DOA10(RAM_DP_0_1_14_DOA10),
	.DOA11(RAM_DP_0_1_14_DOA11),
	.DOA12(RAM_DP_0_1_14_DOA12),
	.DOA13(RAM_DP_0_1_14_DOA13),
	.DOA14(RAM_DP_0_1_14_DOA14),
	.DOA15(RAM_DP_0_1_14_DOA15),
	.DOA16(RAM_DP_0_1_14_DOA16),
	.DOA17(RAM_DP_0_1_14_DOA17),
	.DOB0(Q_c[2]),
	.DOB1(Q_c[3]),
	.DOB2(RAM_DP_0_1_14_DOB2),
	.DOB3(RAM_DP_0_1_14_DOB3),
	.DOB4(RAM_DP_0_1_14_DOB4),
	.DOB5(RAM_DP_0_1_14_DOB5),
	.DOB6(RAM_DP_0_1_14_DOB6),
	.DOB7(RAM_DP_0_1_14_DOB7),
	.DOB8(RAM_DP_0_1_14_DOB8),
	.DOB9(RAM_DP_0_1_14_DOB9),
	.DOB10(RAM_DP_0_1_14_DOB10),
	.DOB11(RAM_DP_0_1_14_DOB11),
	.DOB12(RAM_DP_0_1_14_DOB12),
	.DOB13(RAM_DP_0_1_14_DOB13),
	.DOB14(RAM_DP_0_1_14_DOB14),
	.DOB15(RAM_DP_0_1_14_DOB15),
	.DOB16(RAM_DP_0_1_14_DOB16),
	.DOB17(RAM_DP_0_1_14_DOB17)
);
defparam RAM_DP_0_1_14_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_1_14_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_1_14_Z.RESETMODE="SYNC";
defparam RAM_DP_0_1_14_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_1_14_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_1_14_Z.GSR="ENABLED";
// @4:36
  DP16KB RAM_DP_0_0_15_Z (
	.DIA0(GND),
	.DIA1(Data_c[1]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[0]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),