ram_dp.vm

DDR2 的控制器

	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_10_5_DOA0),
	.DOA1(RAM_DP_0_10_5_DOA1),
	.DOA2(RAM_DP_0_10_5_DOA2),
	.DOA3(RAM_DP_0_10_5_DOA3),
	.DOA4(RAM_DP_0_10_5_DOA4),
	.DOA5(RAM_DP_0_10_5_DOA5),
	.DOA6(RAM_DP_0_10_5_DOA6),
	.DOA7(RAM_DP_0_10_5_DOA7),
	.DOA8(RAM_DP_0_10_5_DOA8),
	.DOA9(RAM_DP_0_10_5_DOA9),
	.DOA10(RAM_DP_0_10_5_DOA10),
	.DOA11(RAM_DP_0_10_5_DOA11),
	.DOA12(RAM_DP_0_10_5_DOA12),
	.DOA13(RAM_DP_0_10_5_DOA13),
	.DOA14(RAM_DP_0_10_5_DOA14),
	.DOA15(RAM_DP_0_10_5_DOA15),
	.DOA16(RAM_DP_0_10_5_DOA16),
	.DOA17(RAM_DP_0_10_5_DOA17),
	.DOB0(Q_c[20]),
	.DOB1(Q_c[21]),
	.DOB2(RAM_DP_0_10_5_DOB2),
	.DOB3(RAM_DP_0_10_5_DOB3),
	.DOB4(RAM_DP_0_10_5_DOB4),
	.DOB5(RAM_DP_0_10_5_DOB5),
	.DOB6(RAM_DP_0_10_5_DOB6),
	.DOB7(RAM_DP_0_10_5_DOB7),
	.DOB8(RAM_DP_0_10_5_DOB8),
	.DOB9(RAM_DP_0_10_5_DOB9),
	.DOB10(RAM_DP_0_10_5_DOB10),
	.DOB11(RAM_DP_0_10_5_DOB11),
	.DOB12(RAM_DP_0_10_5_DOB12),
	.DOB13(RAM_DP_0_10_5_DOB13),
	.DOB14(RAM_DP_0_10_5_DOB14),
	.DOB15(RAM_DP_0_10_5_DOB15),
	.DOB16(RAM_DP_0_10_5_DOB16),
	.DOB17(RAM_DP_0_10_5_DOB17)
);
defparam RAM_DP_0_10_5_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_10_5_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_10_5_Z.RESETMODE="SYNC";
defparam RAM_DP_0_10_5_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_10_5_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_10_5_Z.GSR="ENABLED";
// @4:495
  DP16KB RAM_DP_0_9_6_Z (
	.DIA0(GND),
	.DIA1(Data_c[19]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[18]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_9_6_DOA0),
	.DOA1(RAM_DP_0_9_6_DOA1),
	.DOA2(RAM_DP_0_9_6_DOA2),
	.DOA3(RAM_DP_0_9_6_DOA3),
	.DOA4(RAM_DP_0_9_6_DOA4),
	.DOA5(RAM_DP_0_9_6_DOA5),
	.DOA6(RAM_DP_0_9_6_DOA6),
	.DOA7(RAM_DP_0_9_6_DOA7),
	.DOA8(RAM_DP_0_9_6_DOA8),
	.DOA9(RAM_DP_0_9_6_DOA9),
	.DOA10(RAM_DP_0_9_6_DOA10),
	.DOA11(RAM_DP_0_9_6_DOA11),
	.DOA12(RAM_DP_0_9_6_DOA12),
	.DOA13(RAM_DP_0_9_6_DOA13),
	.DOA14(RAM_DP_0_9_6_DOA14),
	.DOA15(RAM_DP_0_9_6_DOA15),
	.DOA16(RAM_DP_0_9_6_DOA16),
	.DOA17(RAM_DP_0_9_6_DOA17),
	.DOB0(Q_c[18]),
	.DOB1(Q_c[19]),
	.DOB2(RAM_DP_0_9_6_DOB2),
	.DOB3(RAM_DP_0_9_6_DOB3),
	.DOB4(RAM_DP_0_9_6_DOB4),
	.DOB5(RAM_DP_0_9_6_DOB5),
	.DOB6(RAM_DP_0_9_6_DOB6),
	.DOB7(RAM_DP_0_9_6_DOB7),
	.DOB8(RAM_DP_0_9_6_DOB8),
	.DOB9(RAM_DP_0_9_6_DOB9),
	.DOB10(RAM_DP_0_9_6_DOB10),
	.DOB11(RAM_DP_0_9_6_DOB11),
	.DOB12(RAM_DP_0_9_6_DOB12),
	.DOB13(RAM_DP_0_9_6_DOB13),
	.DOB14(RAM_DP_0_9_6_DOB14),
	.DOB15(RAM_DP_0_9_6_DOB15),
	.DOB16(RAM_DP_0_9_6_DOB16),
	.DOB17(RAM_DP_0_9_6_DOB17)
);
defparam RAM_DP_0_9_6_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_9_6_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_9_6_Z.RESETMODE="SYNC";
defparam RAM_DP_0_9_6_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_9_6_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_9_6_Z.GSR="ENABLED";
// @4:444
  DP16KB RAM_DP_0_8_7_Z (
	.DIA0(GND),
	.DIA1(Data_c[17]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[16]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_8_7_DOA0),
	.DOA1(RAM_DP_0_8_7_DOA1),
	.DOA2(RAM_DP_0_8_7_DOA2),
	.DOA3(RAM_DP_0_8_7_DOA3),
	.DOA4(RAM_DP_0_8_7_DOA4),
	.DOA5(RAM_DP_0_8_7_DOA5),
	.DOA6(RAM_DP_0_8_7_DOA6),
	.DOA7(RAM_DP_0_8_7_DOA7),
	.DOA8(RAM_DP_0_8_7_DOA8),
	.DOA9(RAM_DP_0_8_7_DOA9),
	.DOA10(RAM_DP_0_8_7_DOA10),
	.DOA11(RAM_DP_0_8_7_DOA11),
	.DOA12(RAM_DP_0_8_7_DOA12),
	.DOA13(RAM_DP_0_8_7_DOA13),
	.DOA14(RAM_DP_0_8_7_DOA14),
	.DOA15(RAM_DP_0_8_7_DOA15),
	.DOA16(RAM_DP_0_8_7_DOA16),
	.DOA17(RAM_DP_0_8_7_DOA17),
	.DOB0(Q_c[16]),
	.DOB1(Q_c[17]),
	.DOB2(RAM_DP_0_8_7_DOB2),
	.DOB3(RAM_DP_0_8_7_DOB3),
	.DOB4(RAM_DP_0_8_7_DOB4),
	.DOB5(RAM_DP_0_8_7_DOB5),
	.DOB6(RAM_DP_0_8_7_DOB6),
	.DOB7(RAM_DP_0_8_7_DOB7),
	.DOB8(RAM_DP_0_8_7_DOB8),
	.DOB9(RAM_DP_0_8_7_DOB9),
	.DOB10(RAM_DP_0_8_7_DOB10),
	.DOB11(RAM_DP_0_8_7_DOB11),
	.DOB12(RAM_DP_0_8_7_DOB12),
	.DOB13(RAM_DP_0_8_7_DOB13),
	.DOB14(RAM_DP_0_8_7_DOB14),
	.DOB15(RAM_DP_0_8_7_DOB15),
	.DOB16(RAM_DP_0_8_7_DOB16),
	.DOB17(RAM_DP_0_8_7_DOB17)
);
defparam RAM_DP_0_8_7_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_8_7_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_8_7_Z.RESETMODE="SYNC";
defparam RAM_DP_0_8_7_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_8_7_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_8_7_Z.GSR="ENABLED";
// @4:393
  DP16KB RAM_DP_0_7_8_Z (
	.DIA0(GND),
	.DIA1(Data_c[15]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[14]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_7_8_DOA0),
	.DOA1(RAM_DP_0_7_8_DOA1),
	.DOA2(RAM_DP_0_7_8_DOA2),
	.DOA3(RAM_DP_0_7_8_DOA3),
	.DOA4(RAM_DP_0_7_8_DOA4),
	.DOA5(RAM_DP_0_7_8_DOA5),
	.DOA6(RAM_DP_0_7_8_DOA6),
	.DOA7(RAM_DP_0_7_8_DOA7),
	.DOA8(RAM_DP_0_7_8_DOA8),
	.DOA9(RAM_DP_0_7_8_DOA9),
	.DOA10(RAM_DP_0_7_8_DOA10),
	.DOA11(RAM_DP_0_7_8_DOA11),
	.DOA12(RAM_DP_0_7_8_DOA12),
	.DOA13(RAM_DP_0_7_8_DOA13),
	.DOA14(RAM_DP_0_7_8_DOA14),
	.DOA15(RAM_DP_0_7_8_DOA15),
	.DOA16(RAM_DP_0_7_8_DOA16),
	.DOA17(RAM_DP_0_7_8_DOA17),
	.DOB0(Q_c[14]),
	.DOB1(Q_c[15]),
	.DOB2(RAM_DP_0_7_8_DOB2),
	.DOB3(RAM_DP_0_7_8_DOB3),
	.DOB4(RAM_DP_0_7_8_DOB4),
	.DOB5(RAM_DP_0_7_8_DOB5),
	.DOB6(RAM_DP_0_7_8_DOB6),
	.DOB7(RAM_DP_0_7_8_DOB7),
	.DOB8(RAM_DP_0_7_8_DOB8),
	.DOB9(RAM_DP_0_7_8_DOB9),
	.DOB10(RAM_DP_0_7_8_DOB10),
	.DOB11(RAM_DP_0_7_8_DOB11),
	.DOB12(RAM_DP_0_7_8_DOB12),
	.DOB13(RAM_DP_0_7_8_DOB13),
	.DOB14(RAM_DP_0_7_8_DOB14),
	.DOB15(RAM_DP_0_7_8_DOB15),
	.DOB16(RAM_DP_0_7_8_DOB16),
	.DOB17(RAM_DP_0_7_8_DOB17)
);
defparam RAM_DP_0_7_8_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_7_8_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_7_8_Z.RESETMODE="SYNC";
defparam RAM_DP_0_7_8_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_7_8_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_7_8_Z.GSR="ENABLED";
// @4:342
  DP16KB RAM_DP_0_6_9_Z (
	.DIA0(GND),
	.DIA1(Data_c[13]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[12]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_6_9_DOA0),
	.DOA1(RAM_DP_0_6_9_DOA1),
	.DOA2(RAM_DP_0_6_9_DOA2),
	.DOA3(RAM_DP_0_6_9_DOA3),
	.DOA4(RAM_DP_0_6_9_DOA4),
	.DOA5(RAM_DP_0_6_9_DOA5),
	.DOA6(RAM_DP_0_6_9_DOA6),
	.DOA7(RAM_DP_0_6_9_DOA7),
	.DOA8(RAM_DP_0_6_9_DOA8),
	.DOA9(RAM_DP_0_6_9_DOA9),
	.DOA10(RAM_DP_0_6_9_DOA10),
	.DOA11(RAM_DP_0_6_9_DOA11),
	.DOA12(RAM_DP_0_6_9_DOA12),
	.DOA13(RAM_DP_0_6_9_DOA13),
	.DOA14(RAM_DP_0_6_9_DOA14),
	.DOA15(RAM_DP_0_6_9_DOA15),
	.DOA16(RAM_DP_0_6_9_DOA16),
	.DOA17(RAM_DP_0_6_9_DOA17),
	.DOB0(Q_c[12]),
	.DOB1(Q_c[13]),
	.DOB2(RAM_DP_0_6_9_DOB2),
	.DOB3(RAM_DP_0_6_9_DOB3),
	.DOB4(RAM_DP_0_6_9_DOB4),
	.DOB5(RAM_DP_0_6_9_DOB5),
	.DOB6(RAM_DP_0_6_9_DOB6),
	.DOB7(RAM_DP_0_6_9_DOB7),
	.DOB8(RAM_DP_0_6_9_DOB8),
	.DOB9(RAM_DP_0_6_9_DOB9),
	.DOB10(RAM_DP_0_6_9_DOB10),
	.DOB11(RAM_DP_0_6_9_DOB11),
	.DOB12(RAM_DP_0_6_9_DOB12),
	.DOB13(RAM_DP_0_6_9_DOB13),
	.DOB14(RAM_DP_0_6_9_DOB14),
	.DOB15(RAM_DP_0_6_9_DOB15),
	.DOB16(RAM_DP_0_6_9_DOB16),
	.DOB17(RAM_DP_0_6_9_DOB17)
);
defparam RAM_DP_0_6_9_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_6_9_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_6_9_Z.RESETMODE="SYNC";
defparam RAM_DP_0_6_9_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_6_9_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_6_9_Z.GSR="ENABLED";
// @4:291
  DP16KB RAM_DP_0_5_10_Z (
	.DIA0(GND),
	.DIA1(Data_c[11]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[10]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),