ram_dp.vm

DDR2 的控制器

	.DOA16(RAM_DP_0_15_0_DOA16),
	.DOA17(RAM_DP_0_15_0_DOA17),
	.DOB0(Q_c[30]),
	.DOB1(Q_c[31]),
	.DOB2(RAM_DP_0_15_0_DOB2),
	.DOB3(RAM_DP_0_15_0_DOB3),
	.DOB4(RAM_DP_0_15_0_DOB4),
	.DOB5(RAM_DP_0_15_0_DOB5),
	.DOB6(RAM_DP_0_15_0_DOB6),
	.DOB7(RAM_DP_0_15_0_DOB7),
	.DOB8(RAM_DP_0_15_0_DOB8),
	.DOB9(RAM_DP_0_15_0_DOB9),
	.DOB10(RAM_DP_0_15_0_DOB10),
	.DOB11(RAM_DP_0_15_0_DOB11),
	.DOB12(RAM_DP_0_15_0_DOB12),
	.DOB13(RAM_DP_0_15_0_DOB13),
	.DOB14(RAM_DP_0_15_0_DOB14),
	.DOB15(RAM_DP_0_15_0_DOB15),
	.DOB16(RAM_DP_0_15_0_DOB16),
	.DOB17(RAM_DP_0_15_0_DOB17)
);
defparam RAM_DP_0_15_0_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_15_0_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_15_0_Z.RESETMODE="SYNC";
defparam RAM_DP_0_15_0_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_15_0_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_15_0_Z.GSR="ENABLED";
// @4:750
  DP16KB RAM_DP_0_14_1_Z (
	.DIA0(GND),
	.DIA1(Data_c[29]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[28]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_14_1_DOA0),
	.DOA1(RAM_DP_0_14_1_DOA1),
	.DOA2(RAM_DP_0_14_1_DOA2),
	.DOA3(RAM_DP_0_14_1_DOA3),
	.DOA4(RAM_DP_0_14_1_DOA4),
	.DOA5(RAM_DP_0_14_1_DOA5),
	.DOA6(RAM_DP_0_14_1_DOA6),
	.DOA7(RAM_DP_0_14_1_DOA7),
	.DOA8(RAM_DP_0_14_1_DOA8),
	.DOA9(RAM_DP_0_14_1_DOA9),
	.DOA10(RAM_DP_0_14_1_DOA10),
	.DOA11(RAM_DP_0_14_1_DOA11),
	.DOA12(RAM_DP_0_14_1_DOA12),
	.DOA13(RAM_DP_0_14_1_DOA13),
	.DOA14(RAM_DP_0_14_1_DOA14),
	.DOA15(RAM_DP_0_14_1_DOA15),
	.DOA16(RAM_DP_0_14_1_DOA16),
	.DOA17(RAM_DP_0_14_1_DOA17),
	.DOB0(Q_c[28]),
	.DOB1(Q_c[29]),
	.DOB2(RAM_DP_0_14_1_DOB2),
	.DOB3(RAM_DP_0_14_1_DOB3),
	.DOB4(RAM_DP_0_14_1_DOB4),
	.DOB5(RAM_DP_0_14_1_DOB5),
	.DOB6(RAM_DP_0_14_1_DOB6),
	.DOB7(RAM_DP_0_14_1_DOB7),
	.DOB8(RAM_DP_0_14_1_DOB8),
	.DOB9(RAM_DP_0_14_1_DOB9),
	.DOB10(RAM_DP_0_14_1_DOB10),
	.DOB11(RAM_DP_0_14_1_DOB11),
	.DOB12(RAM_DP_0_14_1_DOB12),
	.DOB13(RAM_DP_0_14_1_DOB13),
	.DOB14(RAM_DP_0_14_1_DOB14),
	.DOB15(RAM_DP_0_14_1_DOB15),
	.DOB16(RAM_DP_0_14_1_DOB16),
	.DOB17(RAM_DP_0_14_1_DOB17)
);
defparam RAM_DP_0_14_1_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_14_1_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_14_1_Z.RESETMODE="SYNC";
defparam RAM_DP_0_14_1_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_14_1_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_14_1_Z.GSR="ENABLED";
// @4:699
  DP16KB RAM_DP_0_13_2_Z (
	.DIA0(GND),
	.DIA1(Data_c[27]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[26]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_13_2_DOA0),
	.DOA1(RAM_DP_0_13_2_DOA1),
	.DOA2(RAM_DP_0_13_2_DOA2),
	.DOA3(RAM_DP_0_13_2_DOA3),
	.DOA4(RAM_DP_0_13_2_DOA4),
	.DOA5(RAM_DP_0_13_2_DOA5),
	.DOA6(RAM_DP_0_13_2_DOA6),
	.DOA7(RAM_DP_0_13_2_DOA7),
	.DOA8(RAM_DP_0_13_2_DOA8),
	.DOA9(RAM_DP_0_13_2_DOA9),
	.DOA10(RAM_DP_0_13_2_DOA10),
	.DOA11(RAM_DP_0_13_2_DOA11),
	.DOA12(RAM_DP_0_13_2_DOA12),
	.DOA13(RAM_DP_0_13_2_DOA13),
	.DOA14(RAM_DP_0_13_2_DOA14),
	.DOA15(RAM_DP_0_13_2_DOA15),
	.DOA16(RAM_DP_0_13_2_DOA16),
	.DOA17(RAM_DP_0_13_2_DOA17),
	.DOB0(Q_c[26]),
	.DOB1(Q_c[27]),
	.DOB2(RAM_DP_0_13_2_DOB2),
	.DOB3(RAM_DP_0_13_2_DOB3),
	.DOB4(RAM_DP_0_13_2_DOB4),
	.DOB5(RAM_DP_0_13_2_DOB5),
	.DOB6(RAM_DP_0_13_2_DOB6),
	.DOB7(RAM_DP_0_13_2_DOB7),
	.DOB8(RAM_DP_0_13_2_DOB8),
	.DOB9(RAM_DP_0_13_2_DOB9),
	.DOB10(RAM_DP_0_13_2_DOB10),
	.DOB11(RAM_DP_0_13_2_DOB11),
	.DOB12(RAM_DP_0_13_2_DOB12),
	.DOB13(RAM_DP_0_13_2_DOB13),
	.DOB14(RAM_DP_0_13_2_DOB14),
	.DOB15(RAM_DP_0_13_2_DOB15),
	.DOB16(RAM_DP_0_13_2_DOB16),
	.DOB17(RAM_DP_0_13_2_DOB17)
);
defparam RAM_DP_0_13_2_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_13_2_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_13_2_Z.RESETMODE="SYNC";
defparam RAM_DP_0_13_2_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_13_2_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_13_2_Z.GSR="ENABLED";
// @4:648
  DP16KB RAM_DP_0_12_3_Z (
	.DIA0(GND),
	.DIA1(Data_c[25]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[24]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_12_3_DOA0),
	.DOA1(RAM_DP_0_12_3_DOA1),
	.DOA2(RAM_DP_0_12_3_DOA2),
	.DOA3(RAM_DP_0_12_3_DOA3),
	.DOA4(RAM_DP_0_12_3_DOA4),
	.DOA5(RAM_DP_0_12_3_DOA5),
	.DOA6(RAM_DP_0_12_3_DOA6),
	.DOA7(RAM_DP_0_12_3_DOA7),
	.DOA8(RAM_DP_0_12_3_DOA8),
	.DOA9(RAM_DP_0_12_3_DOA9),
	.DOA10(RAM_DP_0_12_3_DOA10),
	.DOA11(RAM_DP_0_12_3_DOA11),
	.DOA12(RAM_DP_0_12_3_DOA12),
	.DOA13(RAM_DP_0_12_3_DOA13),
	.DOA14(RAM_DP_0_12_3_DOA14),
	.DOA15(RAM_DP_0_12_3_DOA15),
	.DOA16(RAM_DP_0_12_3_DOA16),
	.DOA17(RAM_DP_0_12_3_DOA17),
	.DOB0(Q_c[24]),
	.DOB1(Q_c[25]),
	.DOB2(RAM_DP_0_12_3_DOB2),
	.DOB3(RAM_DP_0_12_3_DOB3),
	.DOB4(RAM_DP_0_12_3_DOB4),
	.DOB5(RAM_DP_0_12_3_DOB5),
	.DOB6(RAM_DP_0_12_3_DOB6),
	.DOB7(RAM_DP_0_12_3_DOB7),
	.DOB8(RAM_DP_0_12_3_DOB8),
	.DOB9(RAM_DP_0_12_3_DOB9),
	.DOB10(RAM_DP_0_12_3_DOB10),
	.DOB11(RAM_DP_0_12_3_DOB11),
	.DOB12(RAM_DP_0_12_3_DOB12),
	.DOB13(RAM_DP_0_12_3_DOB13),
	.DOB14(RAM_DP_0_12_3_DOB14),
	.DOB15(RAM_DP_0_12_3_DOB15),
	.DOB16(RAM_DP_0_12_3_DOB16),
	.DOB17(RAM_DP_0_12_3_DOB17)
);
defparam RAM_DP_0_12_3_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_12_3_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_12_3_Z.RESETMODE="SYNC";
defparam RAM_DP_0_12_3_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_12_3_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_12_3_Z.GSR="ENABLED";
// @4:597
  DP16KB RAM_DP_0_11_4_Z (
	.DIA0(GND),
	.DIA1(Data_c[23]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[22]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_11_4_DOA0),
	.DOA1(RAM_DP_0_11_4_DOA1),
	.DOA2(RAM_DP_0_11_4_DOA2),
	.DOA3(RAM_DP_0_11_4_DOA3),
	.DOA4(RAM_DP_0_11_4_DOA4),
	.DOA5(RAM_DP_0_11_4_DOA5),
	.DOA6(RAM_DP_0_11_4_DOA6),
	.DOA7(RAM_DP_0_11_4_DOA7),
	.DOA8(RAM_DP_0_11_4_DOA8),
	.DOA9(RAM_DP_0_11_4_DOA9),
	.DOA10(RAM_DP_0_11_4_DOA10),
	.DOA11(RAM_DP_0_11_4_DOA11),
	.DOA12(RAM_DP_0_11_4_DOA12),
	.DOA13(RAM_DP_0_11_4_DOA13),
	.DOA14(RAM_DP_0_11_4_DOA14),
	.DOA15(RAM_DP_0_11_4_DOA15),
	.DOA16(RAM_DP_0_11_4_DOA16),
	.DOA17(RAM_DP_0_11_4_DOA17),
	.DOB0(Q_c[22]),
	.DOB1(Q_c[23]),
	.DOB2(RAM_DP_0_11_4_DOB2),
	.DOB3(RAM_DP_0_11_4_DOB3),
	.DOB4(RAM_DP_0_11_4_DOB4),
	.DOB5(RAM_DP_0_11_4_DOB5),
	.DOB6(RAM_DP_0_11_4_DOB6),
	.DOB7(RAM_DP_0_11_4_DOB7),
	.DOB8(RAM_DP_0_11_4_DOB8),
	.DOB9(RAM_DP_0_11_4_DOB9),
	.DOB10(RAM_DP_0_11_4_DOB10),
	.DOB11(RAM_DP_0_11_4_DOB11),
	.DOB12(RAM_DP_0_11_4_DOB12),
	.DOB13(RAM_DP_0_11_4_DOB13),
	.DOB14(RAM_DP_0_11_4_DOB14),
	.DOB15(RAM_DP_0_11_4_DOB15),
	.DOB16(RAM_DP_0_11_4_DOB16),
	.DOB17(RAM_DP_0_11_4_DOB17)
);
defparam RAM_DP_0_11_4_Z.REGMODE_A="OUTREG";
defparam RAM_DP_0_11_4_Z.REGMODE_B="OUTREG";
defparam RAM_DP_0_11_4_Z.RESETMODE="SYNC";
defparam RAM_DP_0_11_4_Z.WRITEMODE_A="NORMAL";
defparam RAM_DP_0_11_4_Z.WRITEMODE_B="NORMAL";
defparam RAM_DP_0_11_4_Z.GSR="ENABLED";
// @4:546
  DP16KB RAM_DP_0_10_5_Z (
	.DIA0(GND),
	.DIA1(Data_c[21]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[20]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),