ram_dp.vm

DDR2 的控制器

wire RdClockEn_c ;
wire Reset_c ;
wire WrClock_c ;
wire WrClockEn_c ;
wire WE_c ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  GSR GSR_INST (
	.GSR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
// @4:19
  OB \Q_pad[31]  (
	.I(Q_c[31]),
	.O(Q[31])
);
// @4:19
  OB \Q_pad[30]  (
	.I(Q_c[30]),
	.O(Q[30])
);
// @4:19
  OB \Q_pad[29]  (
	.I(Q_c[29]),
	.O(Q[29])
);
// @4:19
  OB \Q_pad[28]  (
	.I(Q_c[28]),
	.O(Q[28])
);
// @4:19
  OB \Q_pad[27]  (
	.I(Q_c[27]),
	.O(Q[27])
);
// @4:19
  OB \Q_pad[26]  (
	.I(Q_c[26]),
	.O(Q[26])
);
// @4:19
  OB \Q_pad[25]  (
	.I(Q_c[25]),
	.O(Q[25])
);
// @4:19
  OB \Q_pad[24]  (
	.I(Q_c[24]),
	.O(Q[24])
);
// @4:19
  OB \Q_pad[23]  (
	.I(Q_c[23]),
	.O(Q[23])
);
// @4:19
  OB \Q_pad[22]  (
	.I(Q_c[22]),
	.O(Q[22])
);
// @4:19
  OB \Q_pad[21]  (
	.I(Q_c[21]),
	.O(Q[21])
);
// @4:19
  OB \Q_pad[20]  (
	.I(Q_c[20]),
	.O(Q[20])
);
// @4:19
  OB \Q_pad[19]  (
	.I(Q_c[19]),
	.O(Q[19])
);
// @4:19
  OB \Q_pad[18]  (
	.I(Q_c[18]),
	.O(Q[18])
);
// @4:19
  OB \Q_pad[17]  (
	.I(Q_c[17]),
	.O(Q[17])
);
// @4:19
  OB \Q_pad[16]  (
	.I(Q_c[16]),
	.O(Q[16])
);
// @4:19
  OB \Q_pad[15]  (
	.I(Q_c[15]),
	.O(Q[15])
);
// @4:19
  OB \Q_pad[14]  (
	.I(Q_c[14]),
	.O(Q[14])
);
// @4:19
  OB \Q_pad[13]  (
	.I(Q_c[13]),
	.O(Q[13])
);
// @4:19
  OB \Q_pad[12]  (
	.I(Q_c[12]),
	.O(Q[12])
);
// @4:19
  OB \Q_pad[11]  (
	.I(Q_c[11]),
	.O(Q[11])
);
// @4:19
  OB \Q_pad[10]  (
	.I(Q_c[10]),
	.O(Q[10])
);
// @4:19
  OB \Q_pad[9]  (
	.I(Q_c[9]),
	.O(Q[9])
);
// @4:19
  OB \Q_pad[8]  (
	.I(Q_c[8]),
	.O(Q[8])
);
// @4:19
  OB \Q_pad[7]  (
	.I(Q_c[7]),
	.O(Q[7])
);
// @4:19
  OB \Q_pad[6]  (
	.I(Q_c[6]),
	.O(Q[6])
);
// @4:19
  OB \Q_pad[5]  (
	.I(Q_c[5]),
	.O(Q[5])
);
// @4:19
  OB \Q_pad[4]  (
	.I(Q_c[4]),
	.O(Q[4])
);
// @4:19
  OB \Q_pad[3]  (
	.I(Q_c[3]),
	.O(Q[3])
);
// @4:19
  OB \Q_pad[2]  (
	.I(Q_c[2]),
	.O(Q[2])
);
// @4:19
  OB \Q_pad[1]  (
	.I(Q_c[1]),
	.O(Q[1])
);
// @4:19
  OB \Q_pad[0]  (
	.I(Q_c[0]),
	.O(Q[0])
);
// @4:18
  IB WE_pad (
	.I(WE),
	.O(WE_c)
);
// @4:17
  IB WrClockEn_pad (
	.I(WrClockEn),
	.O(WrClockEn_c)
);
// @4:16
  IB WrClock_pad (
	.I(WrClock),
	.O(WrClock_c)
);
// @4:15
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
// @4:14
  IB RdClockEn_pad (
	.I(RdClockEn),
	.O(RdClockEn_c)
);
// @4:13
  IB RdClock_pad (
	.I(RdClock),
	.O(RdClock_c)
);
// @4:12
  IB \Data_pad[31]  (
	.I(Data[31]),
	.O(Data_c[31])
);
// @4:12
  IB \Data_pad[30]  (
	.I(Data[30]),
	.O(Data_c[30])
);
// @4:12
  IB \Data_pad[29]  (
	.I(Data[29]),
	.O(Data_c[29])
);
// @4:12
  IB \Data_pad[28]  (
	.I(Data[28]),
	.O(Data_c[28])
);
// @4:12
  IB \Data_pad[27]  (
	.I(Data[27]),
	.O(Data_c[27])
);
// @4:12
  IB \Data_pad[26]  (
	.I(Data[26]),
	.O(Data_c[26])
);
// @4:12
  IB \Data_pad[25]  (
	.I(Data[25]),
	.O(Data_c[25])
);
// @4:12
  IB \Data_pad[24]  (
	.I(Data[24]),
	.O(Data_c[24])
);
// @4:12
  IB \Data_pad[23]  (
	.I(Data[23]),
	.O(Data_c[23])
);
// @4:12
  IB \Data_pad[22]  (
	.I(Data[22]),
	.O(Data_c[22])
);
// @4:12
  IB \Data_pad[21]  (
	.I(Data[21]),
	.O(Data_c[21])
);
// @4:12
  IB \Data_pad[20]  (
	.I(Data[20]),
	.O(Data_c[20])
);
// @4:12
  IB \Data_pad[19]  (
	.I(Data[19]),
	.O(Data_c[19])
);
// @4:12
  IB \Data_pad[18]  (
	.I(Data[18]),
	.O(Data_c[18])
);
// @4:12
  IB \Data_pad[17]  (
	.I(Data[17]),
	.O(Data_c[17])
);
// @4:12
  IB \Data_pad[16]  (
	.I(Data[16]),
	.O(Data_c[16])
);
// @4:12
  IB \Data_pad[15]  (
	.I(Data[15]),
	.O(Data_c[15])
);
// @4:12
  IB \Data_pad[14]  (
	.I(Data[14]),
	.O(Data_c[14])
);
// @4:12
  IB \Data_pad[13]  (
	.I(Data[13]),
	.O(Data_c[13])
);
// @4:12
  IB \Data_pad[12]  (
	.I(Data[12]),
	.O(Data_c[12])
);
// @4:12
  IB \Data_pad[11]  (
	.I(Data[11]),
	.O(Data_c[11])
);
// @4:12
  IB \Data_pad[10]  (
	.I(Data[10]),
	.O(Data_c[10])
);
// @4:12
  IB \Data_pad[9]  (
	.I(Data[9]),
	.O(Data_c[9])
);
// @4:12
  IB \Data_pad[8]  (
	.I(Data[8]),
	.O(Data_c[8])
);
// @4:12
  IB \Data_pad[7]  (
	.I(Data[7]),
	.O(Data_c[7])
);
// @4:12
  IB \Data_pad[6]  (
	.I(Data[6]),
	.O(Data_c[6])
);
// @4:12
  IB \Data_pad[5]  (
	.I(Data[5]),
	.O(Data_c[5])
);
// @4:12
  IB \Data_pad[4]  (
	.I(Data[4]),
	.O(Data_c[4])
);
// @4:12
  IB \Data_pad[3]  (
	.I(Data[3]),
	.O(Data_c[3])
);
// @4:12
  IB \Data_pad[2]  (
	.I(Data[2]),
	.O(Data_c[2])
);
// @4:12
  IB \Data_pad[1]  (
	.I(Data[1]),
	.O(Data_c[1])
);
// @4:12
  IB \Data_pad[0]  (
	.I(Data[0]),
	.O(Data_c[0])
);
// @4:11
  IB \RdAddress_pad[12]  (
	.I(RdAddress[12]),
	.O(RdAddress_c[12])
);
// @4:11
  IB \RdAddress_pad[11]  (
	.I(RdAddress[11]),
	.O(RdAddress_c[11])
);
// @4:11
  IB \RdAddress_pad[10]  (
	.I(RdAddress[10]),
	.O(RdAddress_c[10])
);
// @4:11
  IB \RdAddress_pad[9]  (
	.I(RdAddress[9]),
	.O(RdAddress_c[9])
);
// @4:11
  IB \RdAddress_pad[8]  (
	.I(RdAddress[8]),
	.O(RdAddress_c[8])
);
// @4:11
  IB \RdAddress_pad[7]  (
	.I(RdAddress[7]),
	.O(RdAddress_c[7])
);
// @4:11
  IB \RdAddress_pad[6]  (
	.I(RdAddress[6]),
	.O(RdAddress_c[6])
);
// @4:11
  IB \RdAddress_pad[5]  (
	.I(RdAddress[5]),
	.O(RdAddress_c[5])
);
// @4:11
  IB \RdAddress_pad[4]  (
	.I(RdAddress[4]),
	.O(RdAddress_c[4])
);
// @4:11
  IB \RdAddress_pad[3]  (
	.I(RdAddress[3]),
	.O(RdAddress_c[3])
);
// @4:11
  IB \RdAddress_pad[2]  (
	.I(RdAddress[2]),
	.O(RdAddress_c[2])
);
// @4:11
  IB \RdAddress_pad[1]  (
	.I(RdAddress[1]),
	.O(RdAddress_c[1])
);
// @4:11
  IB \RdAddress_pad[0]  (
	.I(RdAddress[0]),
	.O(RdAddress_c[0])
);
// @4:10
  IB \WrAddress_pad[12]  (
	.I(WrAddress[12]),
	.O(WrAddress_c[12])
);
// @4:10
  IB \WrAddress_pad[11]  (
	.I(WrAddress[11]),
	.O(WrAddress_c[11])
);
// @4:10
  IB \WrAddress_pad[10]  (
	.I(WrAddress[10]),
	.O(WrAddress_c[10])
);
// @4:10
  IB \WrAddress_pad[9]  (
	.I(WrAddress[9]),
	.O(WrAddress_c[9])
);
// @4:10
  IB \WrAddress_pad[8]  (
	.I(WrAddress[8]),
	.O(WrAddress_c[8])
);
// @4:10
  IB \WrAddress_pad[7]  (
	.I(WrAddress[7]),
	.O(WrAddress_c[7])
);
// @4:10
  IB \WrAddress_pad[6]  (
	.I(WrAddress[6]),
	.O(WrAddress_c[6])
);
// @4:10
  IB \WrAddress_pad[5]  (
	.I(WrAddress[5]),
	.O(WrAddress_c[5])
);
// @4:10
  IB \WrAddress_pad[4]  (
	.I(WrAddress[4]),
	.O(WrAddress_c[4])
);
// @4:10
  IB \WrAddress_pad[3]  (
	.I(WrAddress[3]),
	.O(WrAddress_c[3])
);
// @4:10
  IB \WrAddress_pad[2]  (
	.I(WrAddress[2]),
	.O(WrAddress_c[2])
);
// @4:10
  IB \WrAddress_pad[1]  (
	.I(WrAddress[1]),
	.O(WrAddress_c[1])
);
// @4:10
  IB \WrAddress_pad[0]  (
	.I(WrAddress[0]),
	.O(WrAddress_c[0])
);
// @4:803
  DP16KB RAM_DP_0_15_0_Z (
	.DIA0(GND),
	.DIA1(Data_c[31]),
	.DIA2(GND),
	.DIA3(GND),
	.DIA4(GND),
	.DIA5(GND),
	.DIA6(GND),
	.DIA7(GND),
	.DIA8(GND),
	.DIA9(GND),
	.DIA10(GND),
	.DIA11(Data_c[30]),
	.DIA12(GND),
	.DIA13(GND),
	.DIA14(GND),
	.DIA15(GND),
	.DIA16(GND),
	.DIA17(GND),
	.ADA0(GND),
	.ADA1(WrAddress_c[0]),
	.ADA2(WrAddress_c[1]),
	.ADA3(WrAddress_c[2]),
	.ADA4(WrAddress_c[3]),
	.ADA5(WrAddress_c[4]),
	.ADA6(WrAddress_c[5]),
	.ADA7(WrAddress_c[6]),
	.ADA8(WrAddress_c[7]),
	.ADA9(WrAddress_c[8]),
	.ADA10(WrAddress_c[9]),
	.ADA11(WrAddress_c[10]),
	.ADA12(WrAddress_c[11]),
	.ADA13(WrAddress_c[12]),
	.CEA(WrClockEn_c),
	.CLKA(WrClock_c),
	.WEA(WE_c),
	.CSA0(GND),
	.CSA1(GND),
	.CSA2(GND),
	.RSTA(Reset_c),
	.DIB0(GND),
	.DIB1(GND),
	.DIB2(GND),
	.DIB3(GND),
	.DIB4(GND),
	.DIB5(GND),
	.DIB6(GND),
	.DIB7(GND),
	.DIB8(GND),
	.DIB9(GND),
	.DIB10(GND),
	.DIB11(GND),
	.DIB12(GND),
	.DIB13(GND),
	.DIB14(GND),
	.DIB15(GND),
	.DIB16(GND),
	.DIB17(GND),
	.ADB0(GND),
	.ADB1(RdAddress_c[0]),
	.ADB2(RdAddress_c[1]),
	.ADB3(RdAddress_c[2]),
	.ADB4(RdAddress_c[3]),
	.ADB5(RdAddress_c[4]),
	.ADB6(RdAddress_c[5]),
	.ADB7(RdAddress_c[6]),
	.ADB8(RdAddress_c[7]),
	.ADB9(RdAddress_c[8]),
	.ADB10(RdAddress_c[9]),
	.ADB11(RdAddress_c[10]),
	.ADB12(RdAddress_c[11]),
	.ADB13(RdAddress_c[12]),
	.CEB(RdClockEn_c),
	.CLKB(RdClock_c),
	.WEB(GND),
	.CSB0(GND),
	.CSB1(GND),
	.CSB2(GND),
	.RSTB(Reset_c),
	.DOA0(RAM_DP_0_15_0_DOA0),
	.DOA1(RAM_DP_0_15_0_DOA1),
	.DOA2(RAM_DP_0_15_0_DOA2),
	.DOA3(RAM_DP_0_15_0_DOA3),
	.DOA4(RAM_DP_0_15_0_DOA4),
	.DOA5(RAM_DP_0_15_0_DOA5),
	.DOA6(RAM_DP_0_15_0_DOA6),
	.DOA7(RAM_DP_0_15_0_DOA7),
	.DOA8(RAM_DP_0_15_0_DOA8),
	.DOA9(RAM_DP_0_15_0_DOA9),
	.DOA10(RAM_DP_0_15_0_DOA10),
	.DOA11(RAM_DP_0_15_0_DOA11),
	.DOA12(RAM_DP_0_15_0_DOA12),
	.DOA13(RAM_DP_0_15_0_DOA13),
	.DOA14(RAM_DP_0_15_0_DOA14),
	.DOA15(RAM_DP_0_15_0_DOA15),