ram_dp.vm

DDR2 的控制器

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Fri Oct 12 15:22:56 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\e:\isptools7_0\synpbase\lib\lucent\ecp2m.v "
// file 2 "\e:\isptools7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v "
// file 3 "\d:\ddr2_s~1\ddr_p_~1\ddr2\impl\ddr2_eval.h "
// file 4 "\d:\ddr2_s~1\ram_dp\ram_dp.v "

`timescale 100 ps/100 ps
module RAM_DP (
  WrAddress,
  RdAddress,
  Data,
  RdClock,
  RdClockEn,
  Reset,
  WrClock,
  WrClockEn,
  WE,
  Q
)
;
input [12:0] WrAddress ;
input [12:0] RdAddress ;
input [31:0] Data ;
input RdClock ;
input RdClockEn ;
input Reset ;
input WrClock ;
input WrClockEn ;
input WE ;
output [31:0] Q ;
wire RdClock ;
wire RdClockEn ;
wire Reset ;
wire WrClock ;
wire WrClockEn ;
wire WE ;
wire [12:0] WrAddress_c;
wire [12:0] RdAddress_c;
wire [31:0] Data_c;
wire [31:0] Q_c;
wire RAM_DP_0_0_15_DOA0 ;
wire RAM_DP_0_0_15_DOA1 ;
wire RAM_DP_0_0_15_DOA2 ;
wire RAM_DP_0_0_15_DOA3 ;
wire RAM_DP_0_0_15_DOA4 ;
wire RAM_DP_0_0_15_DOA5 ;
wire RAM_DP_0_0_15_DOA6 ;
wire RAM_DP_0_0_15_DOA7 ;
wire RAM_DP_0_0_15_DOA8 ;
wire RAM_DP_0_0_15_DOA9 ;
wire RAM_DP_0_0_15_DOA10 ;
wire RAM_DP_0_0_15_DOA11 ;
wire RAM_DP_0_0_15_DOA12 ;
wire RAM_DP_0_0_15_DOA13 ;
wire RAM_DP_0_0_15_DOA14 ;
wire RAM_DP_0_0_15_DOA15 ;
wire RAM_DP_0_0_15_DOA16 ;
wire RAM_DP_0_0_15_DOA17 ;
wire RAM_DP_0_0_15_DOB2 ;
wire RAM_DP_0_0_15_DOB3 ;
wire RAM_DP_0_0_15_DOB4 ;
wire RAM_DP_0_0_15_DOB5 ;
wire RAM_DP_0_0_15_DOB6 ;
wire RAM_DP_0_0_15_DOB7 ;
wire RAM_DP_0_0_15_DOB8 ;
wire RAM_DP_0_0_15_DOB9 ;
wire RAM_DP_0_0_15_DOB10 ;
wire RAM_DP_0_0_15_DOB11 ;
wire RAM_DP_0_0_15_DOB12 ;
wire RAM_DP_0_0_15_DOB13 ;
wire RAM_DP_0_0_15_DOB14 ;
wire RAM_DP_0_0_15_DOB15 ;
wire RAM_DP_0_0_15_DOB16 ;
wire RAM_DP_0_0_15_DOB17 ;
wire RAM_DP_0_1_14_DOA0 ;
wire RAM_DP_0_1_14_DOA1 ;
wire RAM_DP_0_1_14_DOA2 ;
wire RAM_DP_0_1_14_DOA3 ;
wire RAM_DP_0_1_14_DOA4 ;
wire RAM_DP_0_1_14_DOA5 ;
wire RAM_DP_0_1_14_DOA6 ;
wire RAM_DP_0_1_14_DOA7 ;
wire RAM_DP_0_1_14_DOA8 ;
wire RAM_DP_0_1_14_DOA9 ;
wire RAM_DP_0_1_14_DOA10 ;
wire RAM_DP_0_1_14_DOA11 ;
wire RAM_DP_0_1_14_DOA12 ;
wire RAM_DP_0_1_14_DOA13 ;
wire RAM_DP_0_1_14_DOA14 ;
wire RAM_DP_0_1_14_DOA15 ;
wire RAM_DP_0_1_14_DOA16 ;
wire RAM_DP_0_1_14_DOA17 ;
wire RAM_DP_0_1_14_DOB2 ;
wire RAM_DP_0_1_14_DOB3 ;
wire RAM_DP_0_1_14_DOB4 ;
wire RAM_DP_0_1_14_DOB5 ;
wire RAM_DP_0_1_14_DOB6 ;
wire RAM_DP_0_1_14_DOB7 ;
wire RAM_DP_0_1_14_DOB8 ;
wire RAM_DP_0_1_14_DOB9 ;
wire RAM_DP_0_1_14_DOB10 ;
wire RAM_DP_0_1_14_DOB11 ;
wire RAM_DP_0_1_14_DOB12 ;
wire RAM_DP_0_1_14_DOB13 ;
wire RAM_DP_0_1_14_DOB14 ;
wire RAM_DP_0_1_14_DOB15 ;
wire RAM_DP_0_1_14_DOB16 ;
wire RAM_DP_0_1_14_DOB17 ;
wire RAM_DP_0_2_13_DOA0 ;
wire RAM_DP_0_2_13_DOA1 ;
wire RAM_DP_0_2_13_DOA2 ;
wire RAM_DP_0_2_13_DOA3 ;
wire RAM_DP_0_2_13_DOA4 ;
wire RAM_DP_0_2_13_DOA5 ;
wire RAM_DP_0_2_13_DOA6 ;
wire RAM_DP_0_2_13_DOA7 ;
wire RAM_DP_0_2_13_DOA8 ;
wire RAM_DP_0_2_13_DOA9 ;
wire RAM_DP_0_2_13_DOA10 ;
wire RAM_DP_0_2_13_DOA11 ;
wire RAM_DP_0_2_13_DOA12 ;
wire RAM_DP_0_2_13_DOA13 ;
wire RAM_DP_0_2_13_DOA14 ;
wire RAM_DP_0_2_13_DOA15 ;
wire RAM_DP_0_2_13_DOA16 ;
wire RAM_DP_0_2_13_DOA17 ;
wire RAM_DP_0_2_13_DOB2 ;
wire RAM_DP_0_2_13_DOB3 ;
wire RAM_DP_0_2_13_DOB4 ;
wire RAM_DP_0_2_13_DOB5 ;
wire RAM_DP_0_2_13_DOB6 ;
wire RAM_DP_0_2_13_DOB7 ;
wire RAM_DP_0_2_13_DOB8 ;
wire RAM_DP_0_2_13_DOB9 ;
wire RAM_DP_0_2_13_DOB10 ;
wire RAM_DP_0_2_13_DOB11 ;
wire RAM_DP_0_2_13_DOB12 ;
wire RAM_DP_0_2_13_DOB13 ;
wire RAM_DP_0_2_13_DOB14 ;
wire RAM_DP_0_2_13_DOB15 ;
wire RAM_DP_0_2_13_DOB16 ;
wire RAM_DP_0_2_13_DOB17 ;
wire RAM_DP_0_3_12_DOA0 ;
wire RAM_DP_0_3_12_DOA1 ;
wire RAM_DP_0_3_12_DOA2 ;
wire RAM_DP_0_3_12_DOA3 ;
wire RAM_DP_0_3_12_DOA4 ;
wire RAM_DP_0_3_12_DOA5 ;
wire RAM_DP_0_3_12_DOA6 ;
wire RAM_DP_0_3_12_DOA7 ;
wire RAM_DP_0_3_12_DOA8 ;
wire RAM_DP_0_3_12_DOA9 ;
wire RAM_DP_0_3_12_DOA10 ;
wire RAM_DP_0_3_12_DOA11 ;
wire RAM_DP_0_3_12_DOA12 ;
wire RAM_DP_0_3_12_DOA13 ;
wire RAM_DP_0_3_12_DOA14 ;
wire RAM_DP_0_3_12_DOA15 ;
wire RAM_DP_0_3_12_DOA16 ;
wire RAM_DP_0_3_12_DOA17 ;
wire RAM_DP_0_3_12_DOB2 ;
wire RAM_DP_0_3_12_DOB3 ;
wire RAM_DP_0_3_12_DOB4 ;
wire RAM_DP_0_3_12_DOB5 ;
wire RAM_DP_0_3_12_DOB6 ;
wire RAM_DP_0_3_12_DOB7 ;
wire RAM_DP_0_3_12_DOB8 ;
wire RAM_DP_0_3_12_DOB9 ;
wire RAM_DP_0_3_12_DOB10 ;
wire RAM_DP_0_3_12_DOB11 ;
wire RAM_DP_0_3_12_DOB12 ;
wire RAM_DP_0_3_12_DOB13 ;
wire RAM_DP_0_3_12_DOB14 ;
wire RAM_DP_0_3_12_DOB15 ;
wire RAM_DP_0_3_12_DOB16 ;
wire RAM_DP_0_3_12_DOB17 ;
wire RAM_DP_0_4_11_DOA0 ;
wire RAM_DP_0_4_11_DOA1 ;
wire RAM_DP_0_4_11_DOA2 ;
wire RAM_DP_0_4_11_DOA3 ;
wire RAM_DP_0_4_11_DOA4 ;
wire RAM_DP_0_4_11_DOA5 ;
wire RAM_DP_0_4_11_DOA6 ;
wire RAM_DP_0_4_11_DOA7 ;
wire RAM_DP_0_4_11_DOA8 ;
wire RAM_DP_0_4_11_DOA9 ;
wire RAM_DP_0_4_11_DOA10 ;
wire RAM_DP_0_4_11_DOA11 ;
wire RAM_DP_0_4_11_DOA12 ;
wire RAM_DP_0_4_11_DOA13 ;
wire RAM_DP_0_4_11_DOA14 ;
wire RAM_DP_0_4_11_DOA15 ;
wire RAM_DP_0_4_11_DOA16 ;
wire RAM_DP_0_4_11_DOA17 ;
wire RAM_DP_0_4_11_DOB2 ;
wire RAM_DP_0_4_11_DOB3 ;
wire RAM_DP_0_4_11_DOB4 ;
wire RAM_DP_0_4_11_DOB5 ;
wire RAM_DP_0_4_11_DOB6 ;
wire RAM_DP_0_4_11_DOB7 ;
wire RAM_DP_0_4_11_DOB8 ;
wire RAM_DP_0_4_11_DOB9 ;
wire RAM_DP_0_4_11_DOB10 ;
wire RAM_DP_0_4_11_DOB11 ;
wire RAM_DP_0_4_11_DOB12 ;
wire RAM_DP_0_4_11_DOB13 ;
wire RAM_DP_0_4_11_DOB14 ;
wire RAM_DP_0_4_11_DOB15 ;
wire RAM_DP_0_4_11_DOB16 ;
wire RAM_DP_0_4_11_DOB17 ;
wire RAM_DP_0_5_10_DOA0 ;
wire RAM_DP_0_5_10_DOA1 ;
wire RAM_DP_0_5_10_DOA2 ;
wire RAM_DP_0_5_10_DOA3 ;
wire RAM_DP_0_5_10_DOA4 ;
wire RAM_DP_0_5_10_DOA5 ;
wire RAM_DP_0_5_10_DOA6 ;
wire RAM_DP_0_5_10_DOA7 ;
wire RAM_DP_0_5_10_DOA8 ;
wire RAM_DP_0_5_10_DOA9 ;
wire RAM_DP_0_5_10_DOA10 ;
wire RAM_DP_0_5_10_DOA11 ;
wire RAM_DP_0_5_10_DOA12 ;
wire RAM_DP_0_5_10_DOA13 ;
wire RAM_DP_0_5_10_DOA14 ;
wire RAM_DP_0_5_10_DOA15 ;
wire RAM_DP_0_5_10_DOA16 ;
wire RAM_DP_0_5_10_DOA17 ;
wire RAM_DP_0_5_10_DOB2 ;
wire RAM_DP_0_5_10_DOB3 ;
wire RAM_DP_0_5_10_DOB4 ;
wire RAM_DP_0_5_10_DOB5 ;
wire RAM_DP_0_5_10_DOB6 ;
wire RAM_DP_0_5_10_DOB7 ;
wire RAM_DP_0_5_10_DOB8 ;
wire RAM_DP_0_5_10_DOB9 ;
wire RAM_DP_0_5_10_DOB10 ;
wire RAM_DP_0_5_10_DOB11 ;
wire RAM_DP_0_5_10_DOB12 ;
wire RAM_DP_0_5_10_DOB13 ;
wire RAM_DP_0_5_10_DOB14 ;
wire RAM_DP_0_5_10_DOB15 ;
wire RAM_DP_0_5_10_DOB16 ;
wire RAM_DP_0_5_10_DOB17 ;
wire RAM_DP_0_6_9_DOA0 ;
wire RAM_DP_0_6_9_DOA1 ;
wire RAM_DP_0_6_9_DOA2 ;
wire RAM_DP_0_6_9_DOA3 ;
wire RAM_DP_0_6_9_DOA4 ;
wire RAM_DP_0_6_9_DOA5 ;
wire RAM_DP_0_6_9_DOA6 ;
wire RAM_DP_0_6_9_DOA7 ;
wire RAM_DP_0_6_9_DOA8 ;
wire RAM_DP_0_6_9_DOA9 ;
wire RAM_DP_0_6_9_DOA10 ;
wire RAM_DP_0_6_9_DOA11 ;
wire RAM_DP_0_6_9_DOA12 ;
wire RAM_DP_0_6_9_DOA13 ;
wire RAM_DP_0_6_9_DOA14 ;
wire RAM_DP_0_6_9_DOA15 ;
wire RAM_DP_0_6_9_DOA16 ;
wire RAM_DP_0_6_9_DOA17 ;
wire RAM_DP_0_6_9_DOB2 ;
wire RAM_DP_0_6_9_DOB3 ;
wire RAM_DP_0_6_9_DOB4 ;
wire RAM_DP_0_6_9_DOB5 ;
wire RAM_DP_0_6_9_DOB6 ;
wire RAM_DP_0_6_9_DOB7 ;
wire RAM_DP_0_6_9_DOB8 ;
wire RAM_DP_0_6_9_DOB9 ;
wire RAM_DP_0_6_9_DOB10 ;
wire RAM_DP_0_6_9_DOB11 ;
wire RAM_DP_0_6_9_DOB12 ;
wire RAM_DP_0_6_9_DOB13 ;
wire RAM_DP_0_6_9_DOB14 ;
wire RAM_DP_0_6_9_DOB15 ;
wire RAM_DP_0_6_9_DOB16 ;
wire RAM_DP_0_6_9_DOB17 ;
wire RAM_DP_0_7_8_DOA0 ;
wire RAM_DP_0_7_8_DOA1 ;
wire RAM_DP_0_7_8_DOA2 ;
wire RAM_DP_0_7_8_DOA3 ;
wire RAM_DP_0_7_8_DOA4 ;
wire RAM_DP_0_7_8_DOA5 ;
wire RAM_DP_0_7_8_DOA6 ;
wire RAM_DP_0_7_8_DOA7 ;
wire RAM_DP_0_7_8_DOA8 ;
wire RAM_DP_0_7_8_DOA9 ;
wire RAM_DP_0_7_8_DOA10 ;
wire RAM_DP_0_7_8_DOA11 ;
wire RAM_DP_0_7_8_DOA12 ;
wire RAM_DP_0_7_8_DOA13 ;
wire RAM_DP_0_7_8_DOA14 ;
wire RAM_DP_0_7_8_DOA15 ;
wire RAM_DP_0_7_8_DOA16 ;
wire RAM_DP_0_7_8_DOA17 ;
wire RAM_DP_0_7_8_DOB2 ;
wire RAM_DP_0_7_8_DOB3 ;
wire RAM_DP_0_7_8_DOB4 ;
wire RAM_DP_0_7_8_DOB5 ;
wire RAM_DP_0_7_8_DOB6 ;
wire RAM_DP_0_7_8_DOB7 ;
wire RAM_DP_0_7_8_DOB8 ;
wire RAM_DP_0_7_8_DOB9 ;
wire RAM_DP_0_7_8_DOB10 ;
wire RAM_DP_0_7_8_DOB11 ;
wire RAM_DP_0_7_8_DOB12 ;
wire RAM_DP_0_7_8_DOB13 ;
wire RAM_DP_0_7_8_DOB14 ;
wire RAM_DP_0_7_8_DOB15 ;
wire RAM_DP_0_7_8_DOB16 ;
wire RAM_DP_0_7_8_DOB17 ;
wire RAM_DP_0_8_7_DOA0 ;
wire RAM_DP_0_8_7_DOA1 ;
wire RAM_DP_0_8_7_DOA2 ;
wire RAM_DP_0_8_7_DOA3 ;
wire RAM_DP_0_8_7_DOA4 ;
wire RAM_DP_0_8_7_DOA5 ;
wire RAM_DP_0_8_7_DOA6 ;
wire RAM_DP_0_8_7_DOA7 ;
wire RAM_DP_0_8_7_DOA8 ;
wire RAM_DP_0_8_7_DOA9 ;
wire RAM_DP_0_8_7_DOA10 ;
wire RAM_DP_0_8_7_DOA11 ;
wire RAM_DP_0_8_7_DOA12 ;
wire RAM_DP_0_8_7_DOA13 ;
wire RAM_DP_0_8_7_DOA14 ;
wire RAM_DP_0_8_7_DOA15 ;
wire RAM_DP_0_8_7_DOA16 ;
wire RAM_DP_0_8_7_DOA17 ;
wire RAM_DP_0_8_7_DOB2 ;
wire RAM_DP_0_8_7_DOB3 ;
wire RAM_DP_0_8_7_DOB4 ;
wire RAM_DP_0_8_7_DOB5 ;
wire RAM_DP_0_8_7_DOB6 ;
wire RAM_DP_0_8_7_DOB7 ;
wire RAM_DP_0_8_7_DOB8 ;
wire RAM_DP_0_8_7_DOB9 ;
wire RAM_DP_0_8_7_DOB10 ;
wire RAM_DP_0_8_7_DOB11 ;
wire RAM_DP_0_8_7_DOB12 ;
wire RAM_DP_0_8_7_DOB13 ;
wire RAM_DP_0_8_7_DOB14 ;
wire RAM_DP_0_8_7_DOB15 ;
wire RAM_DP_0_8_7_DOB16 ;
wire RAM_DP_0_8_7_DOB17 ;
wire RAM_DP_0_9_6_DOA0 ;
wire RAM_DP_0_9_6_DOA1 ;
wire RAM_DP_0_9_6_DOA2 ;
wire RAM_DP_0_9_6_DOA3 ;
wire RAM_DP_0_9_6_DOA4 ;
wire RAM_DP_0_9_6_DOA5 ;
wire RAM_DP_0_9_6_DOA6 ;
wire RAM_DP_0_9_6_DOA7 ;
wire RAM_DP_0_9_6_DOA8 ;
wire RAM_DP_0_9_6_DOA9 ;
wire RAM_DP_0_9_6_DOA10 ;
wire RAM_DP_0_9_6_DOA11 ;
wire RAM_DP_0_9_6_DOA12 ;
wire RAM_DP_0_9_6_DOA13 ;
wire RAM_DP_0_9_6_DOA14 ;
wire RAM_DP_0_9_6_DOA15 ;
wire RAM_DP_0_9_6_DOA16 ;
wire RAM_DP_0_9_6_DOA17 ;
wire RAM_DP_0_9_6_DOB2 ;
wire RAM_DP_0_9_6_DOB3 ;
wire RAM_DP_0_9_6_DOB4 ;
wire RAM_DP_0_9_6_DOB5 ;
wire RAM_DP_0_9_6_DOB6 ;
wire RAM_DP_0_9_6_DOB7 ;
wire RAM_DP_0_9_6_DOB8 ;
wire RAM_DP_0_9_6_DOB9 ;
wire RAM_DP_0_9_6_DOB10 ;
wire RAM_DP_0_9_6_DOB11 ;
wire RAM_DP_0_9_6_DOB12 ;
wire RAM_DP_0_9_6_DOB13 ;
wire RAM_DP_0_9_6_DOB14 ;
wire RAM_DP_0_9_6_DOB15 ;
wire RAM_DP_0_9_6_DOB16 ;
wire RAM_DP_0_9_6_DOB17 ;
wire RAM_DP_0_10_5_DOA0 ;
wire RAM_DP_0_10_5_DOA1 ;
wire RAM_DP_0_10_5_DOA2 ;
wire RAM_DP_0_10_5_DOA3 ;
wire RAM_DP_0_10_5_DOA4 ;
wire RAM_DP_0_10_5_DOA5 ;
wire RAM_DP_0_10_5_DOA6 ;
wire RAM_DP_0_10_5_DOA7 ;
wire RAM_DP_0_10_5_DOA8 ;
wire RAM_DP_0_10_5_DOA9 ;
wire RAM_DP_0_10_5_DOA10 ;
wire RAM_DP_0_10_5_DOA11 ;
wire RAM_DP_0_10_5_DOA12 ;
wire RAM_DP_0_10_5_DOA13 ;
wire RAM_DP_0_10_5_DOA14 ;
wire RAM_DP_0_10_5_DOA15 ;
wire RAM_DP_0_10_5_DOA16 ;
wire RAM_DP_0_10_5_DOA17 ;
wire RAM_DP_0_10_5_DOB2 ;
wire RAM_DP_0_10_5_DOB3 ;
wire RAM_DP_0_10_5_DOB4 ;
wire RAM_DP_0_10_5_DOB5 ;
wire RAM_DP_0_10_5_DOB6 ;
wire RAM_DP_0_10_5_DOB7 ;
wire RAM_DP_0_10_5_DOB8 ;
wire RAM_DP_0_10_5_DOB9 ;
wire RAM_DP_0_10_5_DOB10 ;
wire RAM_DP_0_10_5_DOB11 ;
wire RAM_DP_0_10_5_DOB12 ;
wire RAM_DP_0_10_5_DOB13 ;
wire RAM_DP_0_10_5_DOB14 ;
wire RAM_DP_0_10_5_DOB15 ;
wire RAM_DP_0_10_5_DOB16 ;
wire RAM_DP_0_10_5_DOB17 ;
wire RAM_DP_0_11_4_DOA0 ;
wire RAM_DP_0_11_4_DOA1 ;
wire RAM_DP_0_11_4_DOA2 ;
wire RAM_DP_0_11_4_DOA3 ;
wire RAM_DP_0_11_4_DOA4 ;
wire RAM_DP_0_11_4_DOA5 ;
wire RAM_DP_0_11_4_DOA6 ;
wire RAM_DP_0_11_4_DOA7 ;
wire RAM_DP_0_11_4_DOA8 ;
wire RAM_DP_0_11_4_DOA9 ;
wire RAM_DP_0_11_4_DOA10 ;
wire RAM_DP_0_11_4_DOA11 ;
wire RAM_DP_0_11_4_DOA12 ;
wire RAM_DP_0_11_4_DOA13 ;
wire RAM_DP_0_11_4_DOA14 ;
wire RAM_DP_0_11_4_DOA15 ;
wire RAM_DP_0_11_4_DOA16 ;
wire RAM_DP_0_11_4_DOA17 ;
wire RAM_DP_0_11_4_DOB2 ;
wire RAM_DP_0_11_4_DOB3 ;
wire RAM_DP_0_11_4_DOB4 ;
wire RAM_DP_0_11_4_DOB5 ;
wire RAM_DP_0_11_4_DOB6 ;
wire RAM_DP_0_11_4_DOB7 ;
wire RAM_DP_0_11_4_DOB8 ;
wire RAM_DP_0_11_4_DOB9 ;
wire RAM_DP_0_11_4_DOB10 ;
wire RAM_DP_0_11_4_DOB11 ;
wire RAM_DP_0_11_4_DOB12 ;
wire RAM_DP_0_11_4_DOB13 ;
wire RAM_DP_0_11_4_DOB14 ;
wire RAM_DP_0_11_4_DOB15 ;
wire RAM_DP_0_11_4_DOB16 ;
wire RAM_DP_0_11_4_DOB17 ;
wire RAM_DP_0_12_3_DOA0 ;
wire RAM_DP_0_12_3_DOA1 ;
wire RAM_DP_0_12_3_DOA2 ;
wire RAM_DP_0_12_3_DOA3 ;
wire RAM_DP_0_12_3_DOA4 ;
wire RAM_DP_0_12_3_DOA5 ;
wire RAM_DP_0_12_3_DOA6 ;
wire RAM_DP_0_12_3_DOA7 ;
wire RAM_DP_0_12_3_DOA8 ;
wire RAM_DP_0_12_3_DOA9 ;
wire RAM_DP_0_12_3_DOA10 ;
wire RAM_DP_0_12_3_DOA11 ;
wire RAM_DP_0_12_3_DOA12 ;
wire RAM_DP_0_12_3_DOA13 ;
wire RAM_DP_0_12_3_DOA14 ;
wire RAM_DP_0_12_3_DOA15 ;
wire RAM_DP_0_12_3_DOA16 ;
wire RAM_DP_0_12_3_DOA17 ;
wire RAM_DP_0_12_3_DOB2 ;
wire RAM_DP_0_12_3_DOB3 ;
wire RAM_DP_0_12_3_DOB4 ;
wire RAM_DP_0_12_3_DOB5 ;
wire RAM_DP_0_12_3_DOB6 ;
wire RAM_DP_0_12_3_DOB7 ;
wire RAM_DP_0_12_3_DOB8 ;
wire RAM_DP_0_12_3_DOB9 ;
wire RAM_DP_0_12_3_DOB10 ;
wire RAM_DP_0_12_3_DOB11 ;
wire RAM_DP_0_12_3_DOB12 ;
wire RAM_DP_0_12_3_DOB13 ;
wire RAM_DP_0_12_3_DOB14 ;
wire RAM_DP_0_12_3_DOB15 ;
wire RAM_DP_0_12_3_DOB16 ;
wire RAM_DP_0_12_3_DOB17 ;
wire RAM_DP_0_13_2_DOA0 ;
wire RAM_DP_0_13_2_DOA1 ;
wire RAM_DP_0_13_2_DOA2 ;
wire RAM_DP_0_13_2_DOA3 ;
wire RAM_DP_0_13_2_DOA4 ;
wire RAM_DP_0_13_2_DOA5 ;
wire RAM_DP_0_13_2_DOA6 ;
wire RAM_DP_0_13_2_DOA7 ;
wire RAM_DP_0_13_2_DOA8 ;
wire RAM_DP_0_13_2_DOA9 ;
wire RAM_DP_0_13_2_DOA10 ;
wire RAM_DP_0_13_2_DOA11 ;
wire RAM_DP_0_13_2_DOA12 ;
wire RAM_DP_0_13_2_DOA13 ;
wire RAM_DP_0_13_2_DOA14 ;
wire RAM_DP_0_13_2_DOA15 ;
wire RAM_DP_0_13_2_DOA16 ;
wire RAM_DP_0_13_2_DOA17 ;
wire RAM_DP_0_13_2_DOB2 ;
wire RAM_DP_0_13_2_DOB3 ;
wire RAM_DP_0_13_2_DOB4 ;
wire RAM_DP_0_13_2_DOB5 ;
wire RAM_DP_0_13_2_DOB6 ;
wire RAM_DP_0_13_2_DOB7 ;
wire RAM_DP_0_13_2_DOB8 ;
wire RAM_DP_0_13_2_DOB9 ;
wire RAM_DP_0_13_2_DOB10 ;
wire RAM_DP_0_13_2_DOB11 ;
wire RAM_DP_0_13_2_DOB12 ;
wire RAM_DP_0_13_2_DOB13 ;
wire RAM_DP_0_13_2_DOB14 ;
wire RAM_DP_0_13_2_DOB15 ;
wire RAM_DP_0_13_2_DOB16 ;
wire RAM_DP_0_13_2_DOB17 ;
wire RAM_DP_0_14_1_DOA0 ;
wire RAM_DP_0_14_1_DOA1 ;
wire RAM_DP_0_14_1_DOA2 ;
wire RAM_DP_0_14_1_DOA3 ;
wire RAM_DP_0_14_1_DOA4 ;
wire RAM_DP_0_14_1_DOA5 ;
wire RAM_DP_0_14_1_DOA6 ;
wire RAM_DP_0_14_1_DOA7 ;
wire RAM_DP_0_14_1_DOA8 ;
wire RAM_DP_0_14_1_DOA9 ;
wire RAM_DP_0_14_1_DOA10 ;
wire RAM_DP_0_14_1_DOA11 ;
wire RAM_DP_0_14_1_DOA12 ;
wire RAM_DP_0_14_1_DOA13 ;
wire RAM_DP_0_14_1_DOA14 ;
wire RAM_DP_0_14_1_DOA15 ;
wire RAM_DP_0_14_1_DOA16 ;
wire RAM_DP_0_14_1_DOA17 ;
wire RAM_DP_0_14_1_DOB2 ;
wire RAM_DP_0_14_1_DOB3 ;
wire RAM_DP_0_14_1_DOB4 ;
wire RAM_DP_0_14_1_DOB5 ;
wire RAM_DP_0_14_1_DOB6 ;
wire RAM_DP_0_14_1_DOB7 ;
wire RAM_DP_0_14_1_DOB8 ;
wire RAM_DP_0_14_1_DOB9 ;
wire RAM_DP_0_14_1_DOB10 ;
wire RAM_DP_0_14_1_DOB11 ;
wire RAM_DP_0_14_1_DOB12 ;
wire RAM_DP_0_14_1_DOB13 ;
wire RAM_DP_0_14_1_DOB14 ;
wire RAM_DP_0_14_1_DOB15 ;
wire RAM_DP_0_14_1_DOB16 ;
wire RAM_DP_0_14_1_DOB17 ;
wire RAM_DP_0_15_0_DOA0 ;
wire RAM_DP_0_15_0_DOA1 ;
wire RAM_DP_0_15_0_DOA2 ;
wire RAM_DP_0_15_0_DOA3 ;
wire RAM_DP_0_15_0_DOA4 ;
wire RAM_DP_0_15_0_DOA5 ;
wire RAM_DP_0_15_0_DOA6 ;
wire RAM_DP_0_15_0_DOA7 ;
wire RAM_DP_0_15_0_DOA8 ;
wire RAM_DP_0_15_0_DOA9 ;
wire RAM_DP_0_15_0_DOA10 ;
wire RAM_DP_0_15_0_DOA11 ;
wire RAM_DP_0_15_0_DOA12 ;
wire RAM_DP_0_15_0_DOA13 ;
wire RAM_DP_0_15_0_DOA14 ;
wire RAM_DP_0_15_0_DOA15 ;
wire RAM_DP_0_15_0_DOA16 ;
wire RAM_DP_0_15_0_DOA17 ;
wire RAM_DP_0_15_0_DOB2 ;
wire RAM_DP_0_15_0_DOB3 ;
wire RAM_DP_0_15_0_DOB4 ;
wire RAM_DP_0_15_0_DOB5 ;
wire RAM_DP_0_15_0_DOB6 ;
wire RAM_DP_0_15_0_DOB7 ;
wire RAM_DP_0_15_0_DOB8 ;
wire RAM_DP_0_15_0_DOB9 ;
wire RAM_DP_0_15_0_DOB10 ;
wire RAM_DP_0_15_0_DOB11 ;
wire RAM_DP_0_15_0_DOB12 ;
wire RAM_DP_0_15_0_DOB13 ;
wire RAM_DP_0_15_0_DOB14 ;
wire RAM_DP_0_15_0_DOB15 ;
wire RAM_DP_0_15_0_DOB16 ;
wire RAM_DP_0_15_0_DOB17 ;
wire GND ;
wire VCC ;
wire RdClock_c ;