ddr_sdram_mem_top.vm

DDR2 的控制器

  dqsin_clk,
  dqs_pio_read,
  em_ddr_dqs,
  ddr_dqs_en_d0,
  dqsdel_0,
  k_clk_c,
  rst_acth
)
;
input [3:2] ddr_dqs_out_d0 ;
output [1:1] data_valid ;
output [1:1] dqsxfer_clk ;
output [1:1] ddrclkpol ;
output [1:1] dqsin_clk ;
input [1:1] dqs_pio_read ;
inout [1:1] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input ddr_dqs_en_d0 ;
input dqsdel_0 ;
input k_clk_c ;
input rst_acth ;
wire ddr_dqs_en_d0 ;
wire dqsdel_0 ;
wire k_clk_c ;
wire rst_acth ;
wire [1:1] dqsi;
wire [1:1] prmbdet;
wire out_to_bb ;
wire tri_en_reg ;
wire rst ;
wire DQSC_1 ;
wire GND ;
wire VCC ;
// @5:179
  BB U1_BB (
	.B(em_ddr_dqs[1]),
	.I(out_to_bb),
	.T(tri_en_reg),
	.O(dqsi[1])
);
//@5:63
// @5:143
  DQSBUFC U1_DQSBUFC (
	.DQSI(dqsi[1]),
	.CLK(k_clk_c),
	.XCLK(k_clk_c),
	.READ(dqs_pio_read[1]),
	.DQSDEL(dqsdel_0),
	.DQSO(dqsin_clk[1]),
	.DDRCLKPOL(ddrclkpol[1]),
	.DQSC(DQSC_1),
	.PRMBDET(prmbdet[1]),
	.DQSXFER(dqsxfer_clk[1]),
	.DATAVALID(data_valid[1])
);
// @5:138
  ODDRXC U1_TODDRXC (
	.DA(ddr_dqs_en_d0),
	.DB(ddr_dqs_en_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(tri_en_reg)
);
// @5:133
  ODDRXC U1_ODDRXC (
	.DA(ddr_dqs_out_d0[3]),
	.DB(ddr_dqs_out_d0[2]),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(out_to_bb)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_dqs_3 */

module ddr_dqs_io (
  em_ddr_dqs,
  dqs_pio_read,
  dqsin_clk,
  ddrclkpol,
  dqsxfer_clk,
  data_valid,
  ddr_dqs_out_d0,
  rst_acth,
  k_clk_c,
  dqsdel_0,
  ddr_dqs_en_d0
)
;
inout [3:0] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input [3:0] dqs_pio_read ;
output [3:0] dqsin_clk ;
output [3:0] ddrclkpol ;
output [3:0] dqsxfer_clk ;
output [3:0] data_valid ;
input [7:0] ddr_dqs_out_d0 ;
input rst_acth ;
input k_clk_c ;
input dqsdel_0 ;
input ddr_dqs_en_d0 ;
wire rst_acth ;
wire k_clk_c ;
wire dqsdel_0 ;
wire ddr_dqs_en_d0 ;
wire GND ;
wire VCC ;
// @5:63
  bidi_dqs \u[0].bidi_dqs  (
	.ddr_dqs_out_d0({ddr_dqs_out_d0[1], ddr_dqs_out_d0[0]}),
	.data_valid(data_valid[0]),
	.dqsxfer_clk(dqsxfer_clk[0]),
	.ddrclkpol(ddrclkpol[0]),
	.dqsin_clk(dqsin_clk[0]),
	.dqs_pio_read(dqs_pio_read[0]),
	.em_ddr_dqs(em_ddr_dqs[0]),
	.ddr_dqs_en_d0(ddr_dqs_en_d0),
	.dqsdel_0(dqsdel_0),
	.k_clk_c(k_clk_c),
	.rst_acth(rst_acth)
);
// @5:63
  bidi_dqs_1 \u[3].bidi_dqs  (
	.ddr_dqs_out_d0({ddr_dqs_out_d0[7], ddr_dqs_out_d0[6]}),
	.data_valid(data_valid[3]),
	.dqsxfer_clk(dqsxfer_clk[3]),
	.ddrclkpol(ddrclkpol[3]),
	.dqsin_clk(dqsin_clk[3]),
	.dqs_pio_read(dqs_pio_read[3]),
	.em_ddr_dqs(em_ddr_dqs[3]),
	.ddr_dqs_en_d0(ddr_dqs_en_d0),
	.dqsdel_0(dqsdel_0),
	.k_clk_c(k_clk_c),
	.rst_acth(rst_acth)
);
// @5:63
  bidi_dqs_2 \u[2].bidi_dqs  (
	.ddr_dqs_out_d0({ddr_dqs_out_d0[5], ddr_dqs_out_d0[4]}),
	.data_valid(data_valid[2]),
	.dqsxfer_clk(dqsxfer_clk[2]),
	.ddrclkpol(ddrclkpol[2]),
	.dqsin_clk(dqsin_clk[2]),
	.dqs_pio_read(dqs_pio_read[2]),
	.em_ddr_dqs(em_ddr_dqs[2]),
	.ddr_dqs_en_d0(ddr_dqs_en_d0),
	.dqsdel_0(dqsdel_0),
	.k_clk_c(k_clk_c),
	.rst_acth(rst_acth)
);
// @5:63
  bidi_dqs_3 \u[1].bidi_dqs  (
	.ddr_dqs_out_d0({ddr_dqs_out_d0[3], ddr_dqs_out_d0[2]}),
	.data_valid(data_valid[1]),
	.dqsxfer_clk(dqsxfer_clk[1]),
	.ddrclkpol(ddrclkpol[1]),
	.dqsin_clk(dqsin_clk[1]),
	.dqs_pio_read(dqs_pio_read[1]),
	.em_ddr_dqs(em_ddr_dqs[1]),
	.ddr_dqs_en_d0(ddr_dqs_en_d0),
	.dqsdel_0(dqsdel_0),
	.k_clk_c(k_clk_c),
	.rst_acth(rst_acth)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* ddr_dqs_io */

module ddr_sdram_mem_io_top (
  ddr_dqs_out_d0,
  data_valid,
  dqs_pio_read,
  em_ddr_dqs,
  ddr_dm_d1,
  em_ddr_dm_c,
  ddr_read_data,
  ddr_write_data_d1,
  em_ddr_data,
  em_ddr_clk_c,
  ddr_dqs_en_d0,
  dqsdel_0,
  ddr_write_data_valid_d0,
  k_clk_c,
  GND,
  VCC,
  em_ddr_odt_c,
  k_clk_c_i,
  ddr_odt_d0,
  rst_acth_0
)
;
input [7:0] ddr_dqs_out_d0 ;
output [3:0] data_valid ;
input [3:0] dqs_pio_read ;
inout [3:0] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input [3:0] ddr_dm_d1 ;
output [1:0] em_ddr_dm_c ;
output [31:0] ddr_read_data ;
input [31:0] ddr_write_data_d1 ;
inout [15:0] em_ddr_data /* synthesis syn_tristate = 1 */;
output [0:0] em_ddr_clk_c ;
input ddr_dqs_en_d0 ;
input dqsdel_0 ;
input ddr_write_data_valid_d0 ;
input k_clk_c ;
input GND ;
input VCC ;
output em_ddr_odt_c ;
input k_clk_c_i ;
input ddr_odt_d0 ;
input rst_acth_0 ;
wire ddr_dqs_en_d0 ;
wire dqsdel_0 ;
wire ddr_write_data_valid_d0 ;
wire k_clk_c ;
wire GND ;
wire VCC ;
wire em_ddr_odt_c ;
wire k_clk_c_i ;
wire ddr_odt_d0 ;
wire rst_acth_0 ;
wire [3:0] dqsxfer_clk;
wire [3:0] dqsin_clk;
wire [3:0] ddrclkpol;
wire rst_acth ;
wire NN_1 ;
wire NN_2 ;
//@11:351
// @9:242
  ODDRXC \U1_ODDR_ODT[0]  (
	.DA(ddr_odt_d0),
	.DB(ddr_odt_d0),
	.CLK(k_clk_c_i),
	.RST(rst_acth),
	.Q(em_ddr_odt_c)
);
// @9:237
  ODDRXC \U1_ODDR_CLK[0]  (
	.DA(VCC),
	.DB(GND),
	.CLK(k_clk_c),
	.RST(rst_acth),
	.Q(em_ddr_clk_c[0])
);
// @9:173
  ddr_data_io U1_ddr_data_io (
	.em_ddr_data({em_ddr_data[15], em_ddr_data[14], em_ddr_data[13], em_ddr_data[12], 
   em_ddr_data[11], em_ddr_data[10], em_ddr_data[9], em_ddr_data[8], em_ddr_data[7], 
   em_ddr_data[6], em_ddr_data[5], em_ddr_data[4], em_ddr_data[3], em_ddr_data[2], 
   em_ddr_data[1], em_ddr_data[0]}),
	.dqsxfer_clk({dqsxfer_clk[3], dqsxfer_clk[2], dqsxfer_clk[1], dqsxfer_clk[0]}),
	.ddr_write_data_d1({ddr_write_data_d1[31], ddr_write_data_d1[30], ddr_write_data_d1[29], 
   ddr_write_data_d1[28], ddr_write_data_d1[27], ddr_write_data_d1[26], 
   ddr_write_data_d1[25], ddr_write_data_d1[24], ddr_write_data_d1[23], 
   ddr_write_data_d1[22], ddr_write_data_d1[21], ddr_write_data_d1[20], 
   ddr_write_data_d1[19], ddr_write_data_d1[18], ddr_write_data_d1[17], 
   ddr_write_data_d1[16], ddr_write_data_d1[15], ddr_write_data_d1[14], 
   ddr_write_data_d1[13], ddr_write_data_d1[12], ddr_write_data_d1[11], 
   ddr_write_data_d1[10], ddr_write_data_d1[9], ddr_write_data_d1[8], 
   ddr_write_data_d1[7], ddr_write_data_d1[6], ddr_write_data_d1[5], ddr_write_data_d1[4], 
   ddr_write_data_d1[3], ddr_write_data_d1[2], ddr_write_data_d1[1], ddr_write_data_d1[0]}),
	.dqsin_clk({dqsin_clk[3], dqsin_clk[2], dqsin_clk[1], dqsin_clk[0]}),
	.ddrclkpol({ddrclkpol[3], ddrclkpol[2], ddrclkpol[1], ddrclkpol[0]}),
	.ddr_read_data({ddr_read_data[31], ddr_read_data[30], ddr_read_data[29], 
   ddr_read_data[28], ddr_read_data[27], ddr_read_data[26], ddr_read_data[25], 
   ddr_read_data[24], ddr_read_data[23], ddr_read_data[22], ddr_read_data[21], 
   ddr_read_data[20], ddr_read_data[19], ddr_read_data[18], ddr_read_data[17], 
   ddr_read_data[16], ddr_read_data[15], ddr_read_data[14], ddr_read_data[13], 
   ddr_read_data[12], ddr_read_data[11], ddr_read_data[10], ddr_read_data[9], 
   ddr_read_data[8], ddr_read_data[7], ddr_read_data[6], ddr_read_data[5], 
   ddr_read_data[4], ddr_read_data[3], ddr_read_data[2], ddr_read_data[1], 
   ddr_read_data[0]}),
	.rst_acth(rst_acth),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.k_clk_c(k_clk_c),
	.VCC(VCC)
);
// @9:190
  ddr_dm_io U1_ddr_dm_io (
	.em_ddr_dm_c({em_ddr_dm_c[1], em_ddr_dm_c[0]}),
	.dqsxfer_clk({dqsxfer_clk[1], dqsxfer_clk[0]}),
	.ddr_dm_d1({ddr_dm_d1[3], ddr_dm_d1[2], ddr_dm_d1[1], ddr_dm_d1[0]}),
	.k_clk_c(k_clk_c),
	.rst_acth(rst_acth)
);
// @9:210
  ddr_dqs_io U1_ddr_dqs_io (
	.em_ddr_dqs({em_ddr_dqs[3], em_ddr_dqs[2], em_ddr_dqs[1], em_ddr_dqs[0]}),
	.dqs_pio_read({dqs_pio_read[3], dqs_pio_read[2], dqs_pio_read[1], dqs_pio_read[0]}),
	.dqsin_clk({dqsin_clk[3], dqsin_clk[2], dqsin_clk[1], dqsin_clk[0]}),
	.ddrclkpol({ddrclkpol[3], ddrclkpol[2], ddrclkpol[1], ddrclkpol[0]}),
	.dqsxfer_clk({dqsxfer_clk[3], dqsxfer_clk[2], dqsxfer_clk[1], dqsxfer_clk[0]}),
	.data_valid({data_valid[3], data_valid[2], data_valid[1], data_valid[0]}),
	.ddr_dqs_out_d0({ddr_dqs_out_d0[7], ddr_dqs_out_d0[6], ddr_dqs_out_d0[5], 
   ddr_dqs_out_d0[4], ddr_dqs_out_d0[3], ddr_dqs_out_d0[2], ddr_dqs_out_d0[1], 
   ddr_dqs_out_d0[0]}),
	.rst_acth(rst_acth),
	.k_clk_c(k_clk_c),
	.dqsdel_0(dqsdel_0),
	.ddr_dqs_en_d0(ddr_dqs_en_d0)
);
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
assign rst_acth = rst_acth_0;
endmodule /* ddr_sdram_mem_io_top */

module pll_266M (
  GND,
  clk_in_c,
  k_clk_c_i,
  k_clk_c
)
;
input GND ;
input clk_in_c ;
output k_clk_c_i ;
output k_clk_c ;
wire GND ;
wire clk_in_c ;
wire k_clk_c_i ;
wire k_clk_c ;
wire CLKOS ;
wire CLKOK ;
wire LOCK_0 ;
wire CLKINTFB ;
wire NN_1 ;
wire VCC ;
// @8:53
  INV k_clk_c_i_cZ (
	.A(k_clk_c),
	.Z(k_clk_c_i)
);
// @4:33
  EHXPLLD PLLDInst_0 (
	.CLKI(clk_in_c),
	.CLKFB(k_clk_c),
	.RST(GND),
	.RSTK(GND),
	.DPAMODE(GND),
	.DRPAI3(GND),
	.DRPAI2(GND),
	.DRPAI1(GND),
	.DRPAI0(GND),
	.DFPAI3(GND),
	.DFPAI2(GND),
	.DFPAI1(GND),
	.DFPAI0(GND),
	.DDAMODE(GND),
	.DDAIZR(GND),
	.DDAILAG(GND),
	.DDAIDEL0(GND),
	.DDAIDEL1(GND),
	.DDAIDEL2(GND),
	.CLKOP(k_clk_c),
	.CLKOS(CLKOS),
	.CLKOK(CLKOK),
	.LOCK(LOCK_0),
	.CLKINTFB(CLKINTFB)
);
defparam PLLDInst_0.FIN = "80.000000";
defparam PLLDInst_0.CLKI_DIV = "3";
defparam PLLDInst_0.CLKFB_DIV = "10";
defparam PLLDInst_0.CLKOP_DIV = "4";
defparam PLLDInst_0.CLKOK_DIV = "2";
defparam PLLDInst_0.FDEL = "0";
defparam PLLDInst_0.PHASEADJ = "0.0";
defparam PLLDInst_0.DUTY = "8";
defparam PLLDInst_0.PHASE_CNTL = "STATIC";
defparam PLLDInst_0.DELAY_CNTL = "STATIC";
defparam PLLDInst_0.CLKOP_BYPASS = "DISABLED";
defparam PLLDInst_0.CLKOS_BYPASS = "DISABLED";
defparam PLLDInst_0.CLKOK_BYPASS = "DISABLED";
  assign NN_1 = 1'b0;
  assign VCC = 1'b1;
endmodule /* pll_266M */

module ddr_sdram_mem_top (
  clk_in,
  rst_n,
  cmd,
  addr,
  cmd_valid,
  init_start,
  write_data,
  data_mask,
  cmd_rdy,
  init_done,
  data_rdy,
  read_data,
  read_data_valid,
  k_clk,
  em_ddr_data,
  em_ddr_dqs,
  em_ddr_clk,
  em_ddr_cke,
  em_ddr_ras_n,
  em_ddr_cas_n,
  em_ddr_we_n,
  em_ddr_cs_n,
  em_ddr_odt,
  em_ddr_dm,
  em_ddr_ba,
  em_ddr_addr
)
;
input clk_in ;
input rst_n ;
input [3:0] cmd ;
input [24:0] addr ;
input cmd_valid ;
input init_start ;
input [31:0] write_data ;
input [3:0] data_mask ;
output cmd_rdy ;
output init_done ;
output data_rdy ;
output [31:0] read_data ;
output read_data_valid ;
output k_clk ;
inout [15:0] em_ddr_data /* synthesis syn_tristate = 1 */;
inout [3:0] em_ddr_dqs /* synthesis syn_tristate = 1 */;
output [0:0] em_ddr_clk ;
output [0:0] em_ddr_cke ;
output em_ddr_ras_n ;
output em_ddr_cas_n ;
output em_ddr_we_n ;
output [0:0] em_ddr_cs_n ;
output em_ddr_odt ;
output [1:0] em_ddr_dm ;
output [1:0] em_ddr_ba ;
output [12:0] em_ddr_addr ;
wire clk_in ;
wire rst_n ;
wire cmd_valid ;
wire init_start ;
wire cmd_rdy ;
wire init_done ;
wire data_rdy ;
wire read_data_valid ;
wire k_clk ;
wire em_ddr_ras_n ;
wire em_ddr_cas_n ;
wire em_ddr_we_n ;
wire em_ddr_odt ;
wire [2:0] cas_latency;
wire [0:0] ddr_cs_n;
wire [2:0] pstd_cas;
wire [2:0] dv_bl_cycles;
wire [12:0] ddr_addr;
wire [1:0] ddr_ba;
wire [1:0] ddr_dqs_out;
wire [31:0] ddr_write_data;
wire [3:0] ddr_dm;
wire [3:0] ddr_dm_d1;
wire [3:0] dqs_pio_read;
wire [7:0] ddr_dqs_out_d0;
wire [31:0] ddr_read_data;
wire [12:0] em_ddr_addr_int;
wire [1:0] em_ddr_ba_int;
wire [0:0] em_ddr_cke_int;
wire [0:0] em_ddr_cs_n_int;
wire [3:0] data_valid;
wire [31:0] ddr_write_data_d1;
wire [3:0] cmd_c;
wire [24:0] addr_c;
wire [31:0] write_data_c;
wire [3:0] data_mask_c;
wire [31:0] read_data_c;
wire [0:0] em_ddr_clk_c;
wire [0:0] em_ddr_cke_c;
wire [0:0] em_ddr_cs_n_c;
wire [1:0] em_ddr_dm_c;
wire [1:0] em_ddr_ba_c;
wire [12:0] em_ddr_addr_c;
wire ddr_cke ;
wire ddr_ras_n ;
wire ddr_cas_n ;
wire ddr_we_n ;
wire ddr_odt ;
wire pio_read ;
wire read_command ;
wire dv_cs_csm_is_rd ;
wire rd_cmd_pulse ;
wire ddr_dqs_en ;
wire ddr_write_data_valid ;
wire ddr_write_data_valid_d1 ;
wire ddr_odt_d0 ;
wire ddr_dqs_en_d0 ;
wire em_ddr_ras_n_int ;
wire em_ddr_we_n_int ;
wire em_ddr_cas_n_int ;
wire ddr_write_data_valid_d0 ;
wire update_cntl ;
wire rst_acth ;
wire dqsdel_0 ;
wire LOCK ;
wire GND ;
wire VCC ;
wire clk_in_c ;
wire rst_n_c ;
wire cmd_valid_c ;
wire init_start_c ;
wire cmd_rdy_c ;
wire init_done_c ;
wire data_rdy_c ;
wire read_data_valid_c ;
wire k_clk_c ;
wire em_ddr_ras_n_c ;
wire em_ddr_cas_n_c ;
wire em_ddr_we_n_c ;
wire em_ddr_odt_c ;
wire k_clk_c_i ;
wire update_cntl_i ;
wire GND_Z ;
wire VCC_Z ;
// @8:53
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
// @8:53
  INV update_cntl_i_cZ (
	.A(update_cntl),
	.Z(update_cntl_i)
);
// @11:391
  OFS1P3BX em_ddr_we_n_0io_Z (
	.D(em_ddr_we_n_int),
	.SP(VCC),
	.SCLK(k_clk_c),
	.PD(GND),
	.Q(em_ddr_we_n_c)
);
// @11:391
  OFS1P3BX em_ddr_ras_n_0io_Z (
	.D(em_ddr_ras_n_int),
	.SP(VCC),
	.SCLK(k_clk_c),
	.PD(GND),
	.Q(em_ddr_ras_n_c)
);
// @11:391
  OFS1P3BX \em_ddr_cs_n_0io_Z[0]  (
	.D(em_ddr_cs_n_int[0]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.PD(GND),
	.Q(em_ddr_cs_n_c[0])
);
// @11:391
  OFS1P3DX \em_ddr_cke_0io_Z[0]  (
	.D(em_ddr_cke_int[0]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_cke_c[0])
);
// @11:391
  OFS1P3BX em_ddr_cas_n_0io_Z (
	.D(em_ddr_cas_n_int),
	.SP(VCC),
	.SCLK(k_clk_c),
	.PD(GND),
	.Q(em_ddr_cas_n_c)
);
// @11:391
  OFS1P3DX \em_ddr_ba_0io_Z[0]  (
	.D(em_ddr_ba_int[0]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_ba_c[0])
);
// @11:391
  OFS1P3DX \em_ddr_ba_0io_Z[1]  (
	.D(em_ddr_ba_int[1]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_ba_c[1])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[0]  (
	.D(em_ddr_addr_int[0]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[0])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[1]  (
	.D(em_ddr_addr_int[1]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[1])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[2]  (
	.D(em_ddr_addr_int[2]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[2])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[3]  (
	.D(em_ddr_addr_int[3]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[3])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[4]  (
	.D(em_ddr_addr_int[4]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[4])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[5]  (
	.D(em_ddr_addr_int[5]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[5])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[6]  (
	.D(em_ddr_addr_int[6]),
	.SP(VCC),
	.SCLK(k_clk_c),
	.CD(GND),
	.Q(em_ddr_addr_c[6])
);
// @11:391
  OFS1P3DX \em_ddr_addr_0io_Z[7]  (