ddr_sdram_mem_top.vm

DDR2 的控制器

  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [3:3] ddrclkpol ;
input [3:3] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [3:3] dqsxfer_clk ;
inout [15:15] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[15]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[3]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[3]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_15 */

module ddr_data_io (
  em_ddr_data,
  dqsxfer_clk,
  ddr_write_data_d1,
  dqsin_clk,
  ddrclkpol,
  ddr_read_data,
  rst_acth,
  ddr_write_data_valid_d0,
  k_clk_c,
  VCC
)
;
inout [15:0] em_ddr_data /* synthesis syn_tristate = 1 */;
input [3:0] dqsxfer_clk ;
input [31:0] ddr_write_data_d1 ;
input [3:0] dqsin_clk ;
input [3:0] ddrclkpol ;
output [31:0] ddr_read_data ;
input rst_acth ;
input ddr_write_data_valid_d0 ;
input k_clk_c ;
input VCC ;
wire rst_acth ;
wire ddr_write_data_valid_d0 ;
wire k_clk_c ;
wire VCC ;
wire GND ;
wire NN_1 ;
// @8:53
  bidi_cell \u[4].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[20]),
	.ddr_read_data_0(ddr_read_data[4]),
	.ddrclkpol(ddrclkpol[1]),
	.dqsin_clk(dqsin_clk[1]),
	.ddr_write_data_d1_16(ddr_write_data_d1[20]),
	.ddr_write_data_d1_0(ddr_write_data_d1[4]),
	.dqsxfer_clk(dqsxfer_clk[1]),
	.em_ddr_data(em_ddr_data[4]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_1 \u[10].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[26]),
	.ddr_read_data_0(ddr_read_data[10]),
	.ddrclkpol(ddrclkpol[2]),
	.dqsin_clk(dqsin_clk[2]),
	.ddr_write_data_d1_16(ddr_write_data_d1[26]),
	.ddr_write_data_d1_0(ddr_write_data_d1[10]),
	.dqsxfer_clk(dqsxfer_clk[2]),
	.em_ddr_data(em_ddr_data[10]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_2 \u[7].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[23]),
	.ddr_read_data_0(ddr_read_data[7]),
	.ddrclkpol(ddrclkpol[1]),
	.dqsin_clk(dqsin_clk[1]),
	.ddr_write_data_d1_16(ddr_write_data_d1[23]),
	.ddr_write_data_d1_0(ddr_write_data_d1[7]),
	.dqsxfer_clk(dqsxfer_clk[1]),
	.em_ddr_data(em_ddr_data[7]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_3 \u[3].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[19]),
	.ddr_read_data_0(ddr_read_data[3]),
	.ddrclkpol(ddrclkpol[0]),
	.dqsin_clk(dqsin_clk[0]),
	.ddr_write_data_d1_16(ddr_write_data_d1[19]),
	.ddr_write_data_d1_0(ddr_write_data_d1[3]),
	.dqsxfer_clk(dqsxfer_clk[0]),
	.em_ddr_data(em_ddr_data[3]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_4 \u[13].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[29]),
	.ddr_read_data_0(ddr_read_data[13]),
	.ddrclkpol(ddrclkpol[3]),
	.dqsin_clk(dqsin_clk[3]),
	.ddr_write_data_d1_16(ddr_write_data_d1[29]),
	.ddr_write_data_d1_0(ddr_write_data_d1[13]),
	.dqsxfer_clk(dqsxfer_clk[3]),
	.em_ddr_data(em_ddr_data[13]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_5 \u[11].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[27]),
	.ddr_read_data_0(ddr_read_data[11]),
	.ddrclkpol(ddrclkpol[2]),
	.dqsin_clk(dqsin_clk[2]),
	.ddr_write_data_d1_16(ddr_write_data_d1[27]),
	.ddr_write_data_d1_0(ddr_write_data_d1[11]),
	.dqsxfer_clk(dqsxfer_clk[2]),
	.em_ddr_data(em_ddr_data[11]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_6 \u[8].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[24]),
	.ddr_read_data_0(ddr_read_data[8]),
	.ddrclkpol(ddrclkpol[2]),
	.dqsin_clk(dqsin_clk[2]),
	.ddr_write_data_d1_16(ddr_write_data_d1[24]),
	.ddr_write_data_d1_0(ddr_write_data_d1[8]),
	.dqsxfer_clk(dqsxfer_clk[2]),
	.em_ddr_data(em_ddr_data[8]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_7 \u[5].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[21]),
	.ddr_read_data_0(ddr_read_data[5]),
	.ddrclkpol(ddrclkpol[1]),
	.dqsin_clk(dqsin_clk[1]),
	.ddr_write_data_d1_16(ddr_write_data_d1[21]),
	.ddr_write_data_d1_0(ddr_write_data_d1[5]),
	.dqsxfer_clk(dqsxfer_clk[1]),
	.em_ddr_data(em_ddr_data[5]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_8 \u[2].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[18]),
	.ddr_read_data_0(ddr_read_data[2]),
	.ddrclkpol(ddrclkpol[0]),
	.dqsin_clk(dqsin_clk[0]),
	.ddr_write_data_d1_16(ddr_write_data_d1[18]),
	.ddr_write_data_d1_0(ddr_write_data_d1[2]),
	.dqsxfer_clk(dqsxfer_clk[0]),
	.em_ddr_data(em_ddr_data[2]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_9 \u[12].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[28]),
	.ddr_read_data_0(ddr_read_data[12]),
	.ddrclkpol(ddrclkpol[3]),
	.dqsin_clk(dqsin_clk[3]),
	.ddr_write_data_d1_16(ddr_write_data_d1[28]),
	.ddr_write_data_d1_0(ddr_write_data_d1[12]),
	.dqsxfer_clk(dqsxfer_clk[3]),
	.em_ddr_data(em_ddr_data[12]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_10 \u[9].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[25]),
	.ddr_read_data_0(ddr_read_data[9]),
	.ddrclkpol(ddrclkpol[2]),
	.dqsin_clk(dqsin_clk[2]),
	.ddr_write_data_d1_16(ddr_write_data_d1[25]),
	.ddr_write_data_d1_0(ddr_write_data_d1[9]),
	.dqsxfer_clk(dqsxfer_clk[2]),
	.em_ddr_data(em_ddr_data[9]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_11 \u[6].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[22]),
	.ddr_read_data_0(ddr_read_data[6]),
	.ddrclkpol(ddrclkpol[1]),
	.dqsin_clk(dqsin_clk[1]),
	.ddr_write_data_d1_16(ddr_write_data_d1[22]),
	.ddr_write_data_d1_0(ddr_write_data_d1[6]),
	.dqsxfer_clk(dqsxfer_clk[1]),
	.em_ddr_data(em_ddr_data[6]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_12 \u[1].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[17]),
	.ddr_read_data_0(ddr_read_data[1]),
	.ddrclkpol(ddrclkpol[0]),
	.dqsin_clk(dqsin_clk[0]),
	.ddr_write_data_d1_16(ddr_write_data_d1[17]),
	.ddr_write_data_d1_0(ddr_write_data_d1[1]),
	.dqsxfer_clk(dqsxfer_clk[0]),
	.em_ddr_data(em_ddr_data[1]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_13 \u[0].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[16]),
	.ddr_read_data_0(ddr_read_data[0]),
	.ddrclkpol(ddrclkpol[0]),
	.dqsin_clk(dqsin_clk[0]),
	.ddr_write_data_d1_16(ddr_write_data_d1[16]),
	.ddr_write_data_d1_0(ddr_write_data_d1[0]),
	.dqsxfer_clk(dqsxfer_clk[0]),
	.em_ddr_data(em_ddr_data[0]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_14 \u[14].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[30]),
	.ddr_read_data_0(ddr_read_data[14]),
	.ddrclkpol(ddrclkpol[3]),
	.dqsin_clk(dqsin_clk[3]),
	.ddr_write_data_d1_16(ddr_write_data_d1[30]),
	.ddr_write_data_d1_0(ddr_write_data_d1[14]),
	.dqsxfer_clk(dqsxfer_clk[3]),
	.em_ddr_data(em_ddr_data[14]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
// @8:53
  bidi_cell_15 \u[15].bidi_cell  (
	.ddr_read_data_16(ddr_read_data[31]),
	.ddr_read_data_0(ddr_read_data[15]),
	.ddrclkpol(ddrclkpol[3]),
	.dqsin_clk(dqsin_clk[3]),
	.ddr_write_data_d1_16(ddr_write_data_d1[31]),
	.ddr_write_data_d1_0(ddr_write_data_d1[15]),
	.dqsxfer_clk(dqsxfer_clk[3]),
	.em_ddr_data(em_ddr_data[15]),
	.VCC(VCC),
	.k_clk_c(k_clk_c),
	.ddr_write_data_valid_d0(ddr_write_data_valid_d0),
	.rst_acth(rst_acth)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
endmodule /* ddr_data_io */

module ddr_dm_io (
  em_ddr_dm_c,
  dqsxfer_clk,
  ddr_dm_d1,
  k_clk_c,
  rst_acth
)
;
output [1:0] em_ddr_dm_c ;
input [1:0] dqsxfer_clk ;
input [3:0] ddr_dm_d1 ;
input k_clk_c ;
input rst_acth ;
wire k_clk_c ;
wire rst_acth ;
wire rst ;
wire GND ;
wire VCC ;
//@9:190
// @7:30
  ODDRMXA \u[1].ODDRB  (
	.DA(ddr_dm_d1[1]),
	.DB(ddr_dm_d1[3]),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(em_ddr_dm_c[1])
);
// @7:30
  ODDRMXA \u[0].ODDRB  (
	.DA(ddr_dm_d1[0]),
	.DB(ddr_dm_d1[2]),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(em_ddr_dm_c[0])
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
assign rst = rst_acth;
endmodule /* ddr_dm_io */

module bidi_dqs (
  ddr_dqs_out_d0,
  data_valid,
  dqsxfer_clk,
  ddrclkpol,
  dqsin_clk,
  dqs_pio_read,
  em_ddr_dqs,
  ddr_dqs_en_d0,
  dqsdel_0,
  k_clk_c,
  rst_acth
)
;
input [1:0] ddr_dqs_out_d0 ;
output [0:0] data_valid ;
output [0:0] dqsxfer_clk ;
output [0:0] ddrclkpol ;
output [0:0] dqsin_clk ;
input [0:0] dqs_pio_read ;
inout [0:0] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input ddr_dqs_en_d0 ;
input dqsdel_0 ;
input k_clk_c ;
input rst_acth ;
wire ddr_dqs_en_d0 ;
wire dqsdel_0 ;
wire k_clk_c ;
wire rst_acth ;
wire [0:0] dqsi;
wire [0:0] prmbdet;
wire out_to_bb ;
wire tri_en_reg ;
wire rst ;
wire DQSC_2 ;
wire GND ;
wire VCC ;
// @5:179
  BB U1_BB (
	.B(em_ddr_dqs[0]),
	.I(out_to_bb),
	.T(tri_en_reg),
	.O(dqsi[0])
);
//@5:63
// @5:143
  DQSBUFC U1_DQSBUFC (
	.DQSI(dqsi[0]),
	.CLK(k_clk_c),
	.XCLK(k_clk_c),
	.READ(dqs_pio_read[0]),
	.DQSDEL(dqsdel_0),
	.DQSO(dqsin_clk[0]),
	.DDRCLKPOL(ddrclkpol[0]),
	.DQSC(DQSC_2),
	.PRMBDET(prmbdet[0]),
	.DQSXFER(dqsxfer_clk[0]),
	.DATAVALID(data_valid[0])
);
// @5:138
  ODDRXC U1_TODDRXC (
	.DA(ddr_dqs_en_d0),
	.DB(ddr_dqs_en_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(tri_en_reg)
);
// @5:133
  ODDRXC U1_ODDRXC (
	.DA(ddr_dqs_out_d0[1]),
	.DB(ddr_dqs_out_d0[0]),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(out_to_bb)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_dqs */

module bidi_dqs_1 (
  ddr_dqs_out_d0,
  data_valid,
  dqsxfer_clk,
  ddrclkpol,
  dqsin_clk,
  dqs_pio_read,
  em_ddr_dqs,
  ddr_dqs_en_d0,
  dqsdel_0,
  k_clk_c,
  rst_acth
)
;
input [7:6] ddr_dqs_out_d0 ;
output [3:3] data_valid ;
output [3:3] dqsxfer_clk ;
output [3:3] ddrclkpol ;
output [3:3] dqsin_clk ;
input [3:3] dqs_pio_read ;
inout [3:3] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input ddr_dqs_en_d0 ;
input dqsdel_0 ;
input k_clk_c ;
input rst_acth ;
wire ddr_dqs_en_d0 ;
wire dqsdel_0 ;
wire k_clk_c ;
wire rst_acth ;
wire [3:3] dqsi;
wire [3:3] prmbdet;
wire out_to_bb ;
wire tri_en_reg ;
wire rst ;
wire DQSC ;
wire GND ;
wire VCC ;
// @5:179
  BB U1_BB (
	.B(em_ddr_dqs[3]),
	.I(out_to_bb),
	.T(tri_en_reg),
	.O(dqsi[3])
);
//@5:63
// @5:143
  DQSBUFC U1_DQSBUFC (
	.DQSI(dqsi[3]),
	.CLK(k_clk_c),
	.XCLK(k_clk_c),
	.READ(dqs_pio_read[3]),
	.DQSDEL(dqsdel_0),
	.DQSO(dqsin_clk[3]),
	.DDRCLKPOL(ddrclkpol[3]),
	.DQSC(DQSC),
	.PRMBDET(prmbdet[3]),
	.DQSXFER(dqsxfer_clk[3]),
	.DATAVALID(data_valid[3])
);
// @5:138
  ODDRXC U1_TODDRXC (
	.DA(ddr_dqs_en_d0),
	.DB(ddr_dqs_en_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(tri_en_reg)
);
// @5:133
  ODDRXC U1_ODDRXC (
	.DA(ddr_dqs_out_d0[7]),
	.DB(ddr_dqs_out_d0[6]),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(out_to_bb)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_dqs_1 */

module bidi_dqs_2 (
  ddr_dqs_out_d0,
  data_valid,
  dqsxfer_clk,
  ddrclkpol,
  dqsin_clk,
  dqs_pio_read,
  em_ddr_dqs,
  ddr_dqs_en_d0,
  dqsdel_0,
  k_clk_c,
  rst_acth
)
;
input [5:4] ddr_dqs_out_d0 ;
output [2:2] data_valid ;
output [2:2] dqsxfer_clk ;
output [2:2] ddrclkpol ;
output [2:2] dqsin_clk ;
input [2:2] dqs_pio_read ;
inout [2:2] em_ddr_dqs /* synthesis syn_tristate = 1 */;
input ddr_dqs_en_d0 ;
input dqsdel_0 ;
input k_clk_c ;
input rst_acth ;
wire ddr_dqs_en_d0 ;
wire dqsdel_0 ;
wire k_clk_c ;
wire rst_acth ;
wire [2:2] dqsi;
wire [2:2] prmbdet;
wire out_to_bb ;
wire tri_en_reg ;
wire rst ;
wire DQSC_0 ;
wire GND ;
wire VCC ;
// @5:179
  BB U1_BB (
	.B(em_ddr_dqs[2]),
	.I(out_to_bb),
	.T(tri_en_reg),
	.O(dqsi[2])
);
//@5:63
// @5:143
  DQSBUFC U1_DQSBUFC (
	.DQSI(dqsi[2]),
	.CLK(k_clk_c),
	.XCLK(k_clk_c),
	.READ(dqs_pio_read[2]),
	.DQSDEL(dqsdel_0),
	.DQSO(dqsin_clk[2]),
	.DDRCLKPOL(ddrclkpol[2]),
	.DQSC(DQSC_0),
	.PRMBDET(prmbdet[2]),
	.DQSXFER(dqsxfer_clk[2]),
	.DATAVALID(data_valid[2])
);
// @5:138
  ODDRXC U1_TODDRXC (
	.DA(ddr_dqs_en_d0),
	.DB(ddr_dqs_en_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(tri_en_reg)
);
// @5:133
  ODDRXC U1_ODDRXC (
	.DA(ddr_dqs_out_d0[5]),
	.DB(ddr_dqs_out_d0[4]),
	.CLK(k_clk_c),
	.RST(rst),
	.Q(out_to_bb)
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_dqs_2 */

module bidi_dqs_3 (
  ddr_dqs_out_d0,
  data_valid,
  dqsxfer_clk,
  ddrclkpol,