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📄 ddr_sdram_mem_top.vm

📁 DDR2 的控制器
💻 VM
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wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[5]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[1]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[1]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_7 */

module bidi_cell_8 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [0:0] ddrclkpol ;
input [0:0] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [0:0] dqsxfer_clk ;
inout [2:2] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[2]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[0]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[0]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_8 */

module bidi_cell_9 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [3:3] ddrclkpol ;
input [3:3] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [3:3] dqsxfer_clk ;
inout [12:12] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[12]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[3]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[3]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_9 */

module bidi_cell_10 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [2:2] ddrclkpol ;
input [2:2] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [2:2] dqsxfer_clk ;
inout [9:9] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[9]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[2]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[2]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_10 */

module bidi_cell_11 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [1:1] ddrclkpol ;
input [1:1] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [1:1] dqsxfer_clk ;
inout [6:6] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[6]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[1]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[1]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_11 */

module bidi_cell_12 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [0:0] ddrclkpol ;
input [0:0] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [0:0] dqsxfer_clk ;
inout [1:1] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[1]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[0]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[0]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_12 */

module bidi_cell_13 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [0:0] ddrclkpol ;
input [0:0] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [0:0] dqsxfer_clk ;
inout [0:0] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[0]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[0]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[0]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_13 */

module bidi_cell_14 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [3:3] ddrclkpol ;
input [3:3] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [3:3] dqsxfer_clk ;
inout [14:14] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[14]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[3]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[3]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_14 */

module bidi_cell_15 (
  ddr_read_data_16,
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