ddr_sdram_mem_top.vm

DDR2 的控制器

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Fri Oct 12 14:50:07 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\e:\isptools7_0\synpbase\lib\lucent\ecp2m.v "
// file 2 "\e:\isptools7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v "
// file 3 "\d:\ddr2_s~1\ddr_p_~1\ddr2\impl\ddr2_eval.h "
// file 4 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\pll_266m.v "
// file 5 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\ddr_dqs_io.v "
// file 6 "\.\ddr_sdram_mem_params.v "
// file 7 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\ddr_dm_io.v "
// file 8 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\ddr_data_io.v "
// file 9 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\ddr_sdram_mem_io_top.v "
// file 10 "\d:\ddr2_s~1\ddr2_bb.v "
// file 11 "\d:\ddr2_s~1\ddr_p_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v "

`timescale 100 ps/100 ps
module bidi_cell (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [1:1] ddrclkpol ;
input [1:1] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [1:1] dqsxfer_clk ;
inout [4:4] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[4]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[1]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[1]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell */

module bidi_cell_1 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [2:2] ddrclkpol ;
input [2:2] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [2:2] dqsxfer_clk ;
inout [10:10] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[10]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[2]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[2]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_1 */

module bidi_cell_2 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [1:1] ddrclkpol ;
input [1:1] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [1:1] dqsxfer_clk ;
inout [7:7] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[7]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[1]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[1]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[1]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_2 */

module bidi_cell_3 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [0:0] ddrclkpol ;
input [0:0] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [0:0] dqsxfer_clk ;
inout [3:3] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[3]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[0]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[0]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[0]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_3 */

module bidi_cell_4 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [3:3] ddrclkpol ;
input [3:3] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [3:3] dqsxfer_clk ;
inout [13:13] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[13]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[3]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[3]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[3]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_4 */

module bidi_cell_5 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [2:2] ddrclkpol ;
input [2:2] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [2:2] dqsxfer_clk ;
inout [11:11] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[11]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[2]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[2]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_5 */

module bidi_cell_6 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [2:2] ddrclkpol ;
input [2:2] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [2:2] dqsxfer_clk ;
inout [8:8] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;
wire k_clk_c ;
wire ddr_write_data_valid_d0 ;
wire rst_acth ;
wire out_to_bb ;
wire out_en_reg ;
wire bb_to_in_tmp ;
wire rst ;
wire GND ;
wire NN_1 ;
// @8:148
  BB U1_BB (
	.B(em_ddr_data[8]),
	.I(out_to_bb),
	.T(out_en_reg),
	.O(bb_to_in_tmp)
);
//@8:53
// @8:136
  ODDRMXA U1_TODDRMXA (
	.DA(ddr_write_data_valid_d0),
	.DB(ddr_write_data_valid_d0),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_en_reg)
);
// @8:129
  ODDRMXA U1_ODDRMXA (
	.DA(ddr_write_data_d1_0),
	.DB(ddr_write_data_d1_16),
	.CLK(k_clk_c),
	.RST(rst),
	.DQSXFER(dqsxfer_clk[2]),
	.Q(out_to_bb)
);
// @8:122
  IDDRMFX1A U1_IDDRMFX1A (
	.D(bb_to_in_tmp),
	.ECLK(dqsin_clk[2]),
	.CLK1(k_clk_c),
	.CLK2(k_clk_c),
	.RST(rst),
	.CE(VCC),
	.DDRCLKPOL(ddrclkpol[2]),
	.QA(ddr_read_data_0),
	.QB(ddr_read_data_16)
);
  assign GND = 1'b0;
  assign NN_1 = 1'b1;
assign rst = rst_acth;
endmodule /* bidi_cell_6 */

module bidi_cell_7 (
  ddr_read_data_16,
  ddr_read_data_0,
  ddrclkpol,
  dqsin_clk,
  ddr_write_data_d1_16,
  ddr_write_data_d1_0,
  dqsxfer_clk,
  em_ddr_data,
  VCC,
  k_clk_c,
  ddr_write_data_valid_d0,
  rst_acth
)
;
output ddr_read_data_16 ;
output ddr_read_data_0 ;
input [1:1] ddrclkpol ;
input [1:1] dqsin_clk ;
input ddr_write_data_d1_16 ;
input ddr_write_data_d1_0 ;
input [1:1] dqsxfer_clk ;
inout [5:5] em_ddr_data /* synthesis syn_tristate = 1 */;
input VCC ;
input k_clk_c ;
input ddr_write_data_valid_d0 ;
input rst_acth ;
wire ddr_read_data_16 ;
wire ddr_read_data_0 ;
wire ddr_write_data_d1_16 ;
wire ddr_write_data_d1_0 ;
wire VCC ;