ddr_sdram_mem_top.edi

DDR2 的控制器

(edif ddr_sdram_mem_top
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2007 10 12 14 50 6)
      (author "Synplicity, Inc.")
      (program "Synplify" (version "Version 8.8L2, mapper 8.8.0, Build 018R"))
     )
   )
  (library LUCENT
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell BB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port B (direction INOUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell OB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell IB (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell OFS1P3DX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port SP (direction INPUT))
           (port SCLK (direction INPUT))
           (port CD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell OFS1P3BX (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port SP (direction INPUT))
           (port SCLK (direction INPUT))
           (port PD (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell PUR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port PUR (direction INPUT))
         )
       )
    )
    (cell GSR (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port GSR (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A (direction INPUT))
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell VHI (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Z (direction OUTPUT))
         )
       )
    )
    (cell VLO (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Z (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell DQSBUFC (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port DQSI (direction INPUT))
           (port CLK (direction INPUT))
           (port XCLK (direction INPUT))
           (port READ (direction INPUT))
           (port DQSDEL (direction INPUT))
           (port DQSO (direction OUTPUT))
           (port DDRCLKPOL (direction OUTPUT))
           (port DQSC (direction OUTPUT))
           (port PRMBDET (direction OUTPUT))
           (port DQSXFER (direction OUTPUT))
           (port DATAVALID (direction OUTPUT))
         )
        (property DQS_LO_DEL_ADJ (string "PLUS"))
        (property DQS_LO_DEL_VAL (string "0"))
        (property DQS_LI_DEL_ADJ (string "MINUS"))
        (property DQS_LI_DEL_VAL (string "4"))
       )
    )
    (cell IDDRMFX1A (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port ECLK (direction INPUT))
           (port CLK1 (direction INPUT))
           (port CLK2 (direction INPUT))
           (port RST (direction INPUT))
           (port CE (direction INPUT))
           (port DDRCLKPOL (direction INPUT))
           (port QA (direction OUTPUT))
           (port QB (direction OUTPUT))
         )
       )
    )
    (cell ODDRMXA (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port DA (direction INPUT))
           (port DB (direction INPUT))
           (port CLK (direction INPUT))
           (port RST (direction INPUT))
           (port DQSXFER (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell ODDRXC (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port DA (direction INPUT))
           (port DB (direction INPUT))
           (port CLK (direction INPUT))
           (port RST (direction INPUT))
           (port Q (direction OUTPUT))
         )
       )
    )
    (cell bidi_dqs_3 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename ddr_dqs_out_d0 "ddr_dqs_out_d0[3:2]") 2) (direction INPUT))
           (port (array (rename data_valid "data_valid[1:1]") 1) (direction OUTPUT))
           (port (array (rename dqsxfer_clk "dqsxfer_clk[1:1]") 1) (direction OUTPUT))
           (port (array (rename ddrclkpol "ddrclkpol[1:1]") 1) (direction OUTPUT))
           (port (array (rename dqsin_clk "dqsin_clk[1:1]") 1) (direction OUTPUT))
           (port (array (rename dqs_pio_read "dqs_pio_read[1:1]") 1) (direction INPUT))
           (port (array (rename em_ddr_dqs "em_ddr_dqs[1:1]") 1) (direction INOUT))
           (port ddr_dqs_en_d0 (direction INPUT))
           (port dqsdel_0 (direction INPUT))
           (port k_clk_c (direction INPUT))
           (port rst_acth (direction INPUT))
         )
         (contents
          (instance U1_BB (viewRef PRIM (cellRef BB (libraryRef LUCENT)))
          )
          (instance U1_DQSBUFC (viewRef verilog (cellRef DQSBUFC))          )
          (instance U1_TODDRXC (viewRef verilog (cellRef ODDRXC))
           (property CLKMODE (string "SCLK"))
          )
          (instance U1_ODDRXC (viewRef verilog (cellRef ODDRXC))
           (property CLKMODE (string "SCLK"))
          )
          (net em_ddr_dqs_1 (joined
           (portRef B (instanceRef U1_BB))
           (portRef (member em_ddr_dqs 0))
          ))
          (net out_to_bb (joined
           (portRef Q (instanceRef U1_ODDRXC))
           (portRef I (instanceRef U1_BB))
          ))
          (net tri_en_reg (joined
           (portRef Q (instanceRef U1_TODDRXC))
           (portRef T (instanceRef U1_BB))
          ))
          (net dqsi_1 (joined
           (portRef O (instanceRef U1_BB))
           (portRef DQSI (instanceRef U1_DQSBUFC))
          ))
          (net U1_ODDRXC_kb (joined
           (portRef RST (instanceRef U1_ODDRXC))
           (portRef RST (instanceRef U1_TODDRXC))
           (portRef rst_acth)
           )
          )
          (net k_clk_c (joined
           (portRef k_clk_c)
           (portRef CLK (instanceRef U1_ODDRXC))
           (portRef CLK (instanceRef U1_TODDRXC))
           (portRef XCLK (instanceRef U1_DQSBUFC))
           (portRef CLK (instanceRef U1_DQSBUFC))
          ))
          (net dqs_pio_read_1 (joined
           (portRef (member dqs_pio_read 0))
           (portRef READ (instanceRef U1_DQSBUFC))
          ))
          (net dqsdel_0 (joined
           (portRef dqsdel_0)
           (portRef DQSDEL (instanceRef U1_DQSBUFC))
          ))
          (net dqsin_clk_1 (joined
           (portRef DQSO (instanceRef U1_DQSBUFC))
           (portRef (member dqsin_clk 0))
          ))
          (net ddrclkpol_1 (joined
           (portRef DDRCLKPOL (instanceRef U1_DQSBUFC))
           (portRef (member ddrclkpol 0))
          ))
          (net DQSC_1 (joined
           (portRef DQSC (instanceRef U1_DQSBUFC))
          ))
          (net prmbdet_1 (joined
           (portRef PRMBDET (instanceRef U1_DQSBUFC))
          ))
          (net dqsxfer_clk_1 (joined
           (portRef DQSXFER (instanceRef U1_DQSBUFC))
           (portRef (member dqsxfer_clk 0))
          ))
          (net data_valid_1 (joined
           (portRef DATAVALID (instanceRef U1_DQSBUFC))
           (portRef (member data_valid 0))
          ))
          (net ddr_dqs_en_d0 (joined
           (portRef ddr_dqs_en_d0)
           (portRef DB (instanceRef U1_TODDRXC))
           (portRef DA (instanceRef U1_TODDRXC))
          ))
          (net ddr_dqs_out_d0_3 (joined
           (portRef (member ddr_dqs_out_d0 0))
           (portRef DA (instanceRef U1_ODDRXC))
          ))
          (net ddr_dqs_out_d0_2 (joined
           (portRef (member ddr_dqs_out_d0 1))
           (portRef DB (instanceRef U1_ODDRXC))
          ))
         )
       )
    )
    (cell bidi_dqs_2 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename ddr_dqs_out_d0 "ddr_dqs_out_d0[5:4]") 2) (direction INPUT))
           (port (array (rename data_valid "data_valid[2:2]") 1) (direction OUTPUT))
           (port (array (rename dqsxfer_clk "dqsxfer_clk[2:2]") 1) (direction OUTPUT))
           (port (array (rename ddrclkpol "ddrclkpol[2:2]") 1) (direction OUTPUT))
           (port (array (rename dqsin_clk "dqsin_clk[2:2]") 1) (direction OUTPUT))
           (port (array (rename dqs_pio_read "dqs_pio_read[2:2]") 1) (direction INPUT))
           (port (array (rename em_ddr_dqs "em_ddr_dqs[2:2]") 1) (direction INOUT))
           (port ddr_dqs_en_d0 (direction INPUT))
           (port dqsdel_0 (direction INPUT))
           (port k_clk_c (direction INPUT))
           (port rst_acth (direction INPUT))
         )
         (contents
          (instance U1_BB (viewRef PRIM (cellRef BB (libraryRef LUCENT)))
          )
          (instance U1_DQSBUFC (viewRef verilog (cellRef DQSBUFC))          )
          (instance U1_TODDRXC (viewRef verilog (cellRef ODDRXC))
           (property CLKMODE (string "SCLK"))
          )
          (instance U1_ODDRXC (viewRef verilog (cellRef ODDRXC))
           (property CLKMODE (string "SCLK"))
          )
          (net em_ddr_dqs_2 (joined
           (portRef B (instanceRef U1_BB))
           (portRef (member em_ddr_dqs 0))
          ))
          (net out_to_bb (joined
           (portRef Q (instanceRef U1_ODDRXC))
           (portRef I (instanceRef U1_BB))
          ))
          (net tri_en_reg (joined
           (portRef Q (instanceRef U1_TODDRXC))
           (portRef T (instanceRef U1_BB))
          ))
          (net dqsi_2 (joined
           (portRef O (instanceRef U1_BB))
           (portRef DQSI (instanceRef U1_DQSBUFC))
          ))
          (net U1_ODDRXC_kb (joined
           (portRef RST (instanceRef U1_ODDRXC))
           (portRef RST (instanceRef U1_TODDRXC))
           (portRef rst_acth)
           )
          )
          (net k_clk_c (joined
           (portRef k_clk_c)
           (portRef CLK (instanceRef U1_ODDRXC))
           (portRef CLK (instanceRef U1_TODDRXC))
           (portRef XCLK (instanceRef U1_DQSBUFC))
           (portRef CLK (instanceRef U1_DQSBUFC))
          ))
          (net dqs_pio_read_2 (joined
           (portRef (member dqs_pio_read 0))
           (portRef READ (instanceRef U1_DQSBUFC))
          ))
          (net dqsdel_0 (joined
           (portRef dqsdel_0)
           (portRef DQSDEL (instanceRef U1_DQSBUFC))
          ))
          (net dqsin_clk_2 (joined
           (portRef DQSO (instanceRef U1_DQSBUFC))
           (portRef (member dqsin_clk 0))
          ))
          (net ddrclkpol_2 (joined
           (portRef DDRCLKPOL (instanceRef U1_DQSBUFC))
           (portRef (member ddrclkpol 0))
          ))
          (net DQSC_0 (joined
           (portRef DQSC (instanceRef U1_DQSBUFC))
          ))
          (net prmbdet_2 (joined
           (portRef PRMBDET (instanceRef U1_DQSBUFC))
          ))