ddr_sdram_mem_top.v

DDR2 的控制器

wire                                  em_ddr_we_n_int;
wire                                  em_ddr_cas_n_int;
wire     [`CS_WIDTH-1:0]              em_ddr_cs_n_int;

`ifdef DUMMY_LOGIC
   wire  [`DSIZE -1:0]          write_data_dummy;
	assign write_data_dummy = {write_data, write_data};
`endif
 RAM_DP U1_RAM_DP(
         .WrAddress(), 
         .RdAddress(), 
         .Data(), 
         .RdClock(k_clk), //OUTPUT CLOCK CONTROL
         .RdClockEn(), 
         .Reset(rst_n), 
         .WrClock(F_CLK),//INPUT CLOCK CONTROL
         .WrClockEn(),
         .WE(),
         .Q()
         );
ddr2 U1_ddr_sdram_mem_core (

    .clk                    (k_clk),
    .rst_n                  (rst_n),

    // User Interface control and data Input signals
    .fb_cmd                 (cmd),
    .fb_addr                (addr),
    .fb_cmd_valid           (cmd_valid),
    `ifdef BRST_CNT_EN
    .fb_burst_length        (burst_count),
    `endif
    .fb_init_start          (init_start),
   `ifdef DUMMY_LOGIC
    .fb_write_data          (write_data_dummy),
   `else
    .fb_write_data          (write_data),
   `endif
    .fb_data_mask           (data_mask),
    .cas_latency            (cas_latency),

    // User Interface timing parameter Input signals
    .tras                   (`TRAS),
    .trc                    (`TRC),
    .trcd                   (`TRCD),
    .trrd                   (`TRRD),
    .trfc                   (`TRFC),
    .trp                    (`TRP),
    .tmrd                   (`TMRD),
    .twr                    (`TWR),
    .trefi                  (`TREFI),
    .ar_burst_en            (`AR_BURST_EN),

   `ifdef DDR2_MODE
	   .trtp               (`TRTP),
	   .twtr               (`TWTR),
    .tckp               (`TCKP),
    //Active low enable for DIFF DQS during INIT
    .diff_dqs_en_n      (1'b1),
    .ddr_odt_d0(ddr_odt_d0),
   `else
        .ext_reg_en         (`EXT_REG_EN),
        .fb_burst_term      (burst_term),
   `endif

    `ifdef DDR2_MODE
	.DataRdy2Data	    (`WrRqDDelay),
    `else
    `ifdef ECP_20_ONLY
    `else
      .DataRdy2Data         (`WrRqDDelay),
    `endif
    `endif

    // User Interface Output signals
    .fb_cmd_rdy             (cmd_rdy),
    .fb_data_rdy            (data_rdy),
    .init_done              (init_done),

    // Pio read signal
    .pio_read               (pio_read),
    .read_command           (read_command),
    .dv_bl_cycles           (dv_bl_cycles),
    .dv_cs_csm_is_rd        (dv_cs_csm_is_rd),
    .rd_cmd_pulse           (rd_cmd_pulse),

    // Memory Interface output signals
    .ddr_cke                (ddr_cke),
    .ddr_ras_n              (ddr_ras_n),
    .ddr_cas_n              (ddr_cas_n),
    .ddr_we_n               (ddr_we_n),
    .ddr_cs_n               (ddr_cs_n),

    `ifdef DDR2_MODE
        .ddr_odt            (ddr_odt),
        .pstd_cas           (pstd_cas),
    `endif

    .ddr_dm                 (ddr_dm),
    .ddr_ba                 (ddr_ba),
    .ddr_dqs_out            (ddr_dqs_out),
    .ddr_addr               (ddr_addr),
    .ddr_dqs_out_en         (ddr_dqs_en),
    .ddr_write_valid_early  (ddr_write_data_valid),
    .ddr_write_data         (ddr_write_data),

    .ddr_write_data_valid_d1(ddr_write_data_valid_d1),
    .ddr_dm_d1		    (ddr_dm_d1),
    .dqs_pio_read	    (dqs_pio_read),
    .ddr_dqs_out_d0	    (ddr_dqs_out_d0),
    .ddr_dqs_en_d0	    (ddr_dqs_en_d0),
    .ddr_read_data	    (ddr_read_data),
    .em_ddr_addr	    (em_ddr_addr_int),
    .em_ddr_ba		    (em_ddr_ba_int),
    .em_ddr_cke		    (em_ddr_cke_int),
    .em_ddr_ras_n	    (em_ddr_ras_n_int),
    .em_ddr_we_n	    (em_ddr_we_n_int),
    .em_ddr_cas_n	    (em_ddr_cas_n_int),
    .em_ddr_cs_n	    (em_ddr_cs_n_int),
    .ddr_write_data_valid_d0(ddr_write_data_valid_d0),
    .update_cntl	    (update_cntl),
    .data_valid		    (data_valid),
    .read_data		    (read_data),
    .read_data_valid	    (read_data_valid),
    .ddr_write_data_d1	    (ddr_write_data_d1),
    .read_pulse_tap	    (rd_pls_tp)

);

ddr_sdram_mem_io_top U1_ddr_sdram_mem_io_top(
   // Clock and reset
   .rst_n                   (rst_n),

   // Bi-directional databus to external memory
   .em_ddr_data             (em_ddr_data),
   .em_ddr_dqs              (em_ddr_dqs),

   // Output to External memory
   // SDRAM Address, controls and clock
   .em_ddr_clk              (em_ddr_clk),

   `ifdef DDR2_MODE
       .em_ddr_odt          (em_ddr_odt),
       .ddr_odt_d0          (ddr_odt_d0),
   `else
   `endif

   .em_ddr_dm               (em_ddr_dm),
   .rst_acth                (rst_acth),
   .k_clk                   (k_clk),
   .ddr_write_data_valid_d1(ddr_write_data_valid_d0), 
   .ddr_dm_d1               (ddr_dm_d1),
   .dqs_pio_read            (dqs_pio_read),
   .ddr_dqs_out_d0          (ddr_dqs_out_d0),
   .ddr_dqs_en_d0           (ddr_dqs_en_d0),

   .ddr_read_data           (ddr_read_data),
   .prmbdet                 (prmbdet),
   .dqsi                    (dqsi),
   .dqsdel                  (dqsdel),
   .ddr_write_data_d1       (ddr_write_data_d1),
   .data_valid              (data_valid)

);


// ====================================================================
// Flop the ADDR/CMD
// ====================================================================
always @ (posedge k_clk or negedge rst_n) begin
    if (!rst_n) begin
       em_ddr_cke              <= 'd0;  
       em_ddr_ras_n            <=  1'b1;
       em_ddr_cas_n            <=  1'b1;
       em_ddr_we_n             <=  1'b1;
       em_ddr_ba               <= 'd0;
       em_ddr_addr             <= 'd0;
       em_ddr_cs_n             <= {`CS_WIDTH{1'b1}};
    end
    else begin
       em_ddr_cke              <= em_ddr_cke_int;
       em_ddr_ras_n            <= em_ddr_ras_n_int;
       em_ddr_cas_n            <= em_ddr_cas_n_int;
       em_ddr_we_n             <= em_ddr_we_n_int;
       em_ddr_ba               <= em_ddr_ba_int;
       em_ddr_addr             <= em_ddr_addr_int;
       em_ddr_cs_n             <= em_ddr_cs_n_int;
    end
end

// ====================================================================
// Instiantiate PLL
// ====================================================================
//kbar_clk_pll U1_kbar_clk_pll (.CLK(clk_in), .RESET(1'b0), .CLKOP(k_clk), .LOCK());
pll_266M  pll_266M (
                      .CLK(clk_in), 
                      .CLKOP(k_clk),
                      .CLKOS(), 
                      .CLKOK(), 
                      .LOCK()
                   );

pll_120M (.CLK(clk_in),.CLKOP(F_CLK),.CLKOK(),.LOCK());

`ifdef USE_TWO_DLL

DQSDLL U0_DQSDLL (.CLK(k_clk), .RST(rst_acth), .UDDCNTL(~update_cntl),
                  .DQSDEL(dqsdel_0), .LOCK());

DQSDLL U1_DQSDLL (.CLK(k_clk), .RST(rst_acth), .UDDCNTL(~update_cntl),
                  .DQSDEL(dqsdel_1), .LOCK());

assign dqsdel[`LEFT_DQS-1:0]            = {`LEFT_DQS{dqsdel_0}};
assign dqsdel[`DQS_WIDTH-1:`LEFT_DQS] = {`DQS_WIDTH-`LEFT_DQS{dqsdel_1}};

`else

DQSDLL U0_DQSDLL (.CLK(k_clk), .RST(rst_acth), .UDDCNTL(~update_cntl),
                  .DQSDEL(dqsdel_0), .LOCK());
assign dqsdel = {`DQS_WIDTH{dqsdel_0}};

`endif

// Instantiate an inverter to break the reset path
INV U1_INV (.A(rst_n), .Z(rst_acth));

GSR u1_GSR
  (
   .GSR   (rst_n)
   )/*synthesis syn_noprune=1*/;


endmodule