ddr_sdram_mem_top.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: ddr_sdram_mem_top.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"
module ddr_sdram_mem_top (

   // Clock and reset
   clk_in,
   rst_n,

   // Inputs signals from the User Interface
   cmd,
   addr,
   cmd_valid,
`ifdef BRST_CNT_EN
   burst_count,
 `endif
   init_start,
   write_data,
   data_mask,

   // User Interface Output signals
   cmd_rdy,
   init_done,
   data_rdy,
   read_data,
   read_data_valid,
   k_clk,

   // Bi-directional databus to external memory
   em_ddr_data,
   em_ddr_dqs,

   // Output to External memory
   // SDRAM Address, controls and clock
   em_ddr_clk,
   em_ddr_cke,
   em_ddr_ras_n,
   em_ddr_cas_n,
   em_ddr_we_n,
   em_ddr_cs_n,

   `ifdef DDR2_MODE
       em_ddr_odt,
   `else
       burst_term,
   `endif

   em_ddr_dm,
   em_ddr_ba,
   em_ddr_addr
);
// ====================================================================
// This define is used to support multiple round trip delays
// ====================================================================
`define READ_PULSE_TAP_WIDTH `DQS_WIDTH*3
`define READ_PULSE_TAP `READ_PULSE_TAP_WIDTH'b0
wire [`READ_PULSE_TAP_WIDTH-1:0]  rd_pls_tp = `READ_PULSE_TAP;

//--------Inputs
input                                 clk_in;
input                                 rst_n;
input   [3:0]                       cmd;
input   [`ADDR_WIDTH-1:0]           addr;
input                                 cmd_valid;
input                                 init_start;
`ifdef BRST_CNT_EN
input   [4:0]                       burst_count;
`endif
`ifdef DUMMY_LOGIC
   input   [(`DSIZE/2)-1:0]         write_data;
`else
   input   [`DSIZE-1:0]             write_data;
`endif
input   [`USER_DM-1:0]              data_mask;
                                                      
//--------Outputs
output                                cmd_rdy;
output                                init_done;
output                                data_rdy;
`ifdef DUMMY_LOGIC
   output  [(`DSIZE/2) -1:0]        read_data;
`else
   output  [`DSIZE -1:0]            read_data;
`endif
output                                read_data_valid;
output                                k_clk;
inout  [`DATA_WIDTH-1:0]            em_ddr_data;
inout  [`DQS_WIDTH-1:0]             em_ddr_dqs;
output [`DATA_WIDTH/8-1:0]          em_ddr_dm;
output [`CLKO_WIDTH-1:0]            em_ddr_clk;
output [`CKE_WIDTH-1:0]             em_ddr_cke;
output                                em_ddr_ras_n;
output                                em_ddr_cas_n;
output                                em_ddr_we_n;
output  [`CS_WIDTH-1:0]             em_ddr_cs_n;

`ifdef DDR2_MODE
    `ifdef CS_WIDTH_1
        output                        em_ddr_odt;
    `else
        output  [`CS_WIDTH -1 :0]   em_ddr_odt;
    `endif
`else
    input                             burst_term;
`endif

output  [`ROW_WIDTH-1:0]            em_ddr_addr;
output  [`BNK_WDTH-1:0]             em_ddr_ba;

//-------------------------------
wire                       F_CLK;
//-------------------------------
//------ Regs
wire                                  update_cntl;
wire [`CLKO_WIDTH-1:0]              em_ddr_clk;
wire [`DATA_WIDTH/8-1:0]            em_ddr_dm;
wire    [`DSIZE-1:0]                ddr_write_data_d1;
`ifdef DDR2_MODE
    `ifdef CS_WIDTH_1
        wire                          em_ddr_odt;
    `else
        wire  [`CS_WIDTH -1 :0]     em_ddr_odt;
    `endif
`else
    wire                              burst_term;
`endif
//------ Wires
wire                                  k_clk;
wire    [`DSIZE-1:0]                ddr_read_data;
`ifdef DUMMY_LOGIC
   wire    [(`DSIZE/2) -1:0]        read_data;
`else
   wire    [`DSIZE -1:0]            read_data;
`endif
wire                                  read_data_valid;
wire   [`USER_DM-1:0]               ddr_dm;
wire    [`USER_DM-1:0]              ddr_dm_d1;
wire   [`DSIZE-1:0]                 ddr_write_data;
`ifdef DDR2_MODE
wire   [2:0]                        pstd_cas;
    `ifdef CS_WIDTH_1
        wire                          ddr_odt;
        wire                          ddr_odt_d0;
    `else
        wire    [`CS_WIDTH -1 :0]   ddr_odt;
        wire     [`CS_WIDTH -1 :0]  ddr_odt_d0;
    `endif
`endif
wire                                  pio_read;
wire                                  read_command;
`ifdef DATA_SIZE_8
  `ifdef DQSD_4
    wire   [(`DQS_WIDTH)-1:0]       prmbdet;
    wire   [(`DQS_WIDTH)-1:0]       dqsi;
    wire   [(`DQS_WIDTH)-1:0]       dqsxfer_clk;    
    wire   [(`DQS_WIDTH)-1:0]       dqsin_clk;
  `else
    wire                              prmbdet;
    wire                              dqsi;
    wire                              dqsxfer_clk;
    wire                              dqsin_clk;
  `endif
`else
    wire   [(`DQS_WIDTH)-1:0]       prmbdet;
    wire   [(`DQS_WIDTH)-1:0]       dqsi;
    wire   [(`DQS_WIDTH)-1:0]       dqsxfer_clk;    
    wire   [(`DQS_WIDTH)-1:0]       dqsin_clk;
`endif
`ifdef ECP
   `ifdef DATA_SIZE_8
     `ifdef DQSD_4
        wire    [(`DQS_WIDTH) -1:0]   al_data_valid;
     `else
        wire                            al_data_valid;
     `endif
   `else
      wire    [(`DQS_WIDTH) -1:0]   al_data_valid;
   `endif
`endif
wire                                  dv_cs_csm_is_rd;
wire                                  rd_cmd_pulse;
wire    [2:0]                         dv_bl_cycles;
wire    [2:0]                       cas_latency;
wire    [`ROW_WIDTH-1:0]            ddr_addr;

reg      [`ROW_WIDTH-1:0]             em_ddr_addr/* synthesis dout = "" */;
reg      [`BNK_WDTH-1:0]              em_ddr_ba/* synthesis dout = "" */;
reg      [`CKE_WIDTH-1:0]             em_ddr_cke/* synthesis dout = "" */;
reg                                   em_ddr_ras_n/* synthesis dout = "" */;
reg                                   em_ddr_we_n/* synthesis dout = "" */;
reg                                   em_ddr_cas_n/* synthesis dout = "" */;
reg      [`CS_WIDTH-1:0]              em_ddr_cs_n/* synthesis dout = "" */;
//pragma attribute em_ddr_addr outff true
//pragma attribute em_ddr_ba outff true
//pragma attribute em_ddr_cke outff true
//pragma attribute em_ddr_ras_n outff true
//pragma attribute em_ddr_we_n outff true
//pragma attribute em_ddr_cas_n outff true
//pragma attribute em_ddr_cs_n outff true

wire                                  ddr_write_data_valid_d0;
wire				                      CLKOS;
wire    [`BNK_WDTH-1:0]             ddr_ba;
wire                                  ddr_cke;
wire                                  ddr_ras_n;
wire                                  ddr_we_n;
wire                                  ddr_cas_n;
wire    [`CS_WIDTH-1:0]             ddr_cs_n;
wire    [1:0]                       ddr_dqs_out;
wire     [(2*`DQS_WIDTH)-1:0]       ddr_dqs_out_d0;
wire                                  ddr_dqs_en;
wire                                  ddr_dqs_en_d0;
wire                                  ddr_write_data_valid;
wire                                  ddr_write_data_valid_d1;
wire                                  dqsdel_0,dqsdel_1;
wire          [`DQS_WIDTH-1:0]        dqsdel;
`ifdef DATA_SIZE_8
  `ifdef DQSD_4
    wire  [(`DQS_WIDTH)-1:0]          data_valid;
  `else
    wire                              data_valid;
  `endif
`else
    wire  [(`DQS_WIDTH)-1:0]          data_valid;
`endif
wire    [(`DQS_WIDTH)-1:0]            dqs_pio_read;

wire     [`ROW_WIDTH-1:0]             em_ddr_addr_int;
wire     [`BNK_WDTH-1:0]              em_ddr_ba_int;
wire     [`CKE_WIDTH-1:0]             em_ddr_cke_int;
wire                                  em_ddr_ras_n_int;