g_ele_translate.vhd

电梯控制器 用于八层楼双电梯的协调调度 可进行扩展

      O => g_1_des_one_MUX_BLOCK_N5
    );
  g_1_des_one_floor_0_5 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => g_1_FR_one_state(0),
      ADR1 => g_1_des_one_register_out(4),
      ADR2 => g_1_des_one_register_out(5),
      O => g_1_des_one_MUX_BLOCK_N6
    );
  g_1_des_one_floor_1_rn_1 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N6,
      IB => g_1_des_one_MUX_BLOCK_N5,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF52
    );
  g_1_des_one_floor_0_6 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => g_1_FR_one_state(0),
      ADR1 => g_1_des_one_register_out(2),
      ADR2 => g_1_des_one_register_out(3),
      O => g_1_des_one_MUX_BLOCK_N7
    );
  g_1_des_one_floor_0_7 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => g_1_FR_one_state(0),
      ADR1 => g_1_des_one_register_out(0),
      ADR2 => g_1_des_one_register_out(1),
      O => g_1_des_one_MUX_BLOCK_N8
    );
  g_1_des_one_floor_1_rn_2 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N8,
      IB => g_1_des_one_MUX_BLOCK_N7,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF53
    );
  g_1_des_one_Mmux_n0016_n0016_n0016 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_floor_1_MUXF53,
      IB => g_1_des_one_MUX_BLOCK_floor_1_MUXF52,
      SEL => g_1_FR_one_state(2),
      O => g_1_des_one_n0017
    );
  g_1_des_one_floor_0_8 : X_LUT2
    generic map(
      INIT => X"D"
    )
    port map (
      ADR0 => g_1_des_one_register_out(7),
      ADR1 => g_1_FR_one_state(0),
      O => g_1_des_one_MUX_BLOCK_N9
    );
  g_1_cu_one_n0001_2_13_SW0_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => g_1_cu_one_state(1),
      ADR1 => g_1_cu_one_state(0),
      O => N1717
    );
  g_cu_Mmux_n0008_n0008_0_n0008_0_rn_0 : X_LUT4
    generic map(
      INIT => X"FA72"
    )
    port map (
      ADR0 => g_1_lamp_one_state(1),
      ADR1 => g_cu_n0096(2),
      ADR2 => N1454,
      ADR3 => g_1_lamp_one_state(0),
      O => g_cu_MUX_BLOCK_n0009
    );
  g_cu_Mmux_n0008_n0008_0_n0008_0_rn_0_SW0 : X_LUT4
    generic map(
      INIT => X"01AB"
    )
    port map (
      ADR0 => g_1_lamp_one_state(0),
      ADR1 => re_req_out_1(0),
      ADR2 => re_req_out_1(1),
      ADR3 => g_cu_n0096(1),
      O => N1454
    );
  g_cu_Mmux_n0008_n0008_0_n0008_0_Q : X_LUT4
    generic map(
      INIT => X"FD75"
    )
    port map (
      ADR0 => re_req_out_1(1),
      ADR1 => g_1_lamp_one_state(1),
      ADR2 => N1452,
      ADR3 => g_1_lamp_one_state(0),
      O => g_cu_MUX_BLOCK_n0008(1)
    );
  floor_1_0_OBUF : X_BUF
    port map (
      I => g_1_FR_one_state(0),
      O => floor_1_0_OBUF_GTS_TRI
    );
  g_cu_Mmux_n0003_n0003_n0003_rn_0_SW0 : X_LUT4
    generic map(
      INIT => X"FAF8"
    )
    port map (
      ADR0 => g_2_lamp_one_state(0),
      ADR1 => g_2_des_one_now,
      ADR2 => re_req_out_2(0),
      ADR3 => up_2,
      O => N1456
    );
  g_2_des_one_n01061 : X_LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      ADR0 => N1767,
      ADR1 => g_2_FR_one_state(2),
      ADR2 => g_2_FR_one_state(1),
      ADR3 => load_enable2,
      O => g_2_des_one_n0106
    );
  floor_1_1_OBUF : X_BUF
    port map (
      I => g_1_FR_one_state(1),
      O => floor_1_1_OBUF_GTS_TRI
    );
  g_1_des_one_n00131 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_1_IBUF,
      O => g_1_des_one_n0013
    );
  g_1_des_one_n00031 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_6_IBUF,
      O => g_1_des_one_n0003
    );
  g_1_des_one_n00051 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_5_IBUF,
      O => g_1_des_one_n0005
    );
  g_2_des_one_n01021 : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => load_enable2,
      ADR1 => N1450,
      ADR2 => g_2_FR_one_state(1),
      ADR3 => g_2_FR_one_state(2),
      O => g_2_des_one_n0102
    );
  g_2_cu_one_Ker81_SW1_SW0 : X_LUT2
    generic map(
      INIT => X"2"
    )
    port map (
      ADR0 => g_2_cu_one_state(1),
      ADR1 => re_in_IBUF,
      O => N1715
    );
  g_2_des_one_n00981 : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => load_enable2,
      ADR1 => N1450,
      ADR2 => g_2_FR_one_state(2),
      ADR3 => g_2_FR_one_state(1),
      O => g_2_des_one_n0098
    );
  g_2_des_one_n01041111_G : X_LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1746
    );
  re_n02844_SW01_G : X_LUT3
    generic map(
      INIT => X"DF"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1748
    );
  g_2_des_one_n00941 : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => load_enable2,
      ADR1 => g_2_FR_one_state(2),
      ADR2 => g_2_FR_one_state(1),
      ADR3 => N1450,
      O => g_2_des_one_n0094
    );
  g_cu_mov_2_1 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => N1426,
      SSET => CHOICE1365,
      CLK => call_2,
      O => g_cu_mov_2(1),
      CE => VCC,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  g_2_des_one_n00091 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_3_IBUF,
      O => g_2_des_one_n0009
    );
  d_floor_1_4_OBUF : X_BUF
    port map (
      I => g_1_des_one_register_out_4_1,
      O => d_floor_1_4_OBUF_GTS_TRI
    );
  g_2_des_one_floor_0_11_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => g_2_des_one_register_out(2),
      ADR1 => g_2_des_one_N31,
      O => N1684
    );
  g_2_des_one_n00371 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => g_2_des_one_register_out(4),
      ADR1 => g_2_des_one_register_out(5),
      ADR2 => g_2_des_one_register_out(6),
      ADR3 => g_2_des_one_register_out(7),
      O => g_2_des_one_N31
    );
  g_2_des_one_n00011 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_7_IBUF,
      O => g_2_des_one_n0001
    );
  g_2_des_one_register_out_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_des_one_n0005,
      CE => g_2_des_one_n0096,
      RST => g_2_des_one_register_out_5_GSR_OR,
      CLK => Q_n0009,
      O => g_2_des_one_register_out(5),
      SET => GND
    );
  g_2_des_one_floor_1_rn_3 : X_MUX2
    port map (
      IA => g_2_des_one_MUX_BLOCK_N10,
      IB => g_2_des_one_MUX_BLOCK_N9,
      SEL => g_2_FR_one_state(1),
      O => g_2_des_one_MUX_BLOCK_floor_1_MUXF54
    );
  g_2_des_one_up_5 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N1,
      SRST => g_2_des_one_MUX_BLOCK_n0018,
      CLK => request_2,
      O => g_2_des_one_up,
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  g_2_des_one_now_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_des_one_n0017,
      CLK => request_2,
      O => g_2_des_one_now,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  g_2_des_one_down_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_des_one_n0016,
      CLK => request_2,
      O => g_2_des_one_down,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  g_2_des_one_register_out_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_des_one_n0015,
      CE => g_2_des_one_n0106,
      RST => g_2_des_one_register_out_0_GSR_OR,
      CLK => Q_n0009,
      O => g_2_des_one_register_out(0),
      SET => GND
    );
  g_2_des_one_register_out_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_des_one_n0013,
      CE => g_2_des_one_n0104,
      RST => g_2_des_one_register_out_1_GSR_OR,
      CLK => Q_n0009,
      O => g_2_des_one_register_out(1),
      SET => GND
    );
  floor_1_2_OBUF : X_BUF
    port map (
      I => g_1_FR_one_state(2),
      O => floor_1_2_OBUF_GTS_TRI
    );
  g_2_des_one_floor_0_2 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => g_2_des_one_register_out(1),
      ADR1 => g_2_FR_one_state(0),
      ADR2 => g_2_des_one_register_out(2),
      ADR3 => g_2_des_one_register_out(0),
      O => g_2_des_one_MUX_BLOCK_N3
    );
  re_n02904_SW01_G : X_LUT3
    generic map(
      INIT => X"DF"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1750
    );
  code_0_IBUF_8 : X_BUF
    port map (
      I => code(0),
      O => code_0_IBUF
    );
  g_1_des_one_floor_0_9 : X_LUT4
    generic map(
      INIT => X"1011"
    )
    port map (
      ADR0 => g_1_des_one_register_out(6),
      ADR1 => g_1_des_one_register_out(7),
      ADR2 => g_1_FR_one_state(0),
      ADR3 => g_1_des_one_register_out(5),
      O => g_1_des_one_MUX_BLOCK_N10
    );
  g_2_des_one_n00961111_G : X_LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1752
    );
  g_2_des_one_floor_0_1_SW1 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => g_2_des_one_register_out(2),
      ADR1 => g_2_des_one_register_out(1),
      ADR2 => g_2_des_one_register_out(0),
      O => N1702
    );
  re_n02884_SW01_G : X_LUT3
    generic map(
      INIT => X"DF"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1754
    );
  re_n0