frtest.v

来自「电梯控制器 用于八层楼双电梯的协调调度 可进行扩展」· Verilog 代码 · 共 74 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:26:51 01/26/2007
// Design Name:   FR
// Module Name:   FRtest.v
// Project Name:  lift
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: FR
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module FRtest_v;

	// Inputs
	reg clk;
	reg rst;
	reg [1:0] lamp;
	reg FLE;

	// Outputs
	wire [2:0] FR_out;

	// Instantiate the Unit Under Test (UUT)
	FR uut (
		.clk(clk), 
		.rst(rst), 
		.lamp(lamp), 
		.FLE(FLE), 
		.FR_out(FR_out)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		lamp = 0;
		FLE = 0;

		// Wait 100 ns for global reset to finish
		#100;

		rst = 1;
		# 100 lamp = 'b00;
		# 200 FLE = 'b1;

		# 400 lamp = 'b01;
		# 1000 FLE = 0;
		# 400 FLE = 1;
		# 400 lamp = 'b10;


      # 1000 $stop;  
		// Add stimulus here

	end

	always # 100 clk = ~clk;
      
endmodule