g_ele_translate.vhd

电梯控制器 用于八层楼双电梯的协调调度 可进行扩展

      O => N1462
    );
  g_cu_mov_2_0 : X_SFF
    generic map(
      INIT => '1'
    )
    port map (
      I => N1427,
      SSET => CHOICE1399,
      CLK => call_2,
      O => g_cu_mov_2(0),
      CE => VCC,
      SET => GSR,
      RST => GND,
      SRST => GND
    );
  g_1_des_one_n00091 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_3_IBUF,
      O => g_1_des_one_n0009
    );
  d_floor_1_6_OBUF : X_BUF
    port map (
      I => g_1_des_one_register_out_6_1,
      O => d_floor_1_6_OBUF_GTS_TRI
    );
  g_1_des_one_floor_0_11_SW0 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => g_1_des_one_register_out(2),
      ADR1 => g_1_des_one_N31,
      O => N1682
    );
  g_1_des_one_n00371 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => g_1_des_one_register_out(4),
      ADR1 => g_1_des_one_register_out(5),
      ADR2 => g_1_des_one_register_out(6),
      ADR3 => g_1_des_one_register_out(7),
      O => g_1_des_one_N31
    );
  g_1_des_one_n00011 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_7_IBUF,
      O => g_1_des_one_n0001
    );
  g_1_des_one_register_out_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0005,
      CE => g_1_des_one_n0096,
      RST => g_1_des_one_register_out_5_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(5),
      SET => GND
    );
  g_1_des_one_floor_1_rn_3 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N10,
      IB => g_1_des_one_MUX_BLOCK_N9,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF54
    );
  g_1_des_one_up_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => N1,
      SRST => g_1_des_one_MUX_BLOCK_n0018,
      CLK => request_1,
      O => g_1_des_one_up,
      CE => VCC,
      SET => GND,
      RST => GSR,
      SSET => GND
    );
  g_1_des_one_now_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0017,
      CLK => request_1,
      O => g_1_des_one_now,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  g_1_des_one_down_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0016,
      CLK => request_1,
      O => g_1_des_one_down,
      CE => VCC,
      SET => GND,
      RST => GSR
    );
  g_1_des_one_register_out_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0015,
      CE => g_1_des_one_n0106,
      RST => g_1_des_one_register_out_0_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(0),
      SET => GND
    );
  g_1_des_one_register_out_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0013,
      CE => g_1_des_one_n0104,
      RST => g_1_des_one_register_out_1_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(1),
      SET => GND
    );
  floor_2_1_OBUF : X_BUF
    port map (
      I => g_2_FR_one_state(1),
      O => floor_2_1_OBUF_GTS_TRI
    );
  g_1_des_one_floor_0_2 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => g_1_des_one_register_out(1),
      ADR1 => g_1_FR_one_state(0),
      ADR2 => g_1_des_one_register_out(2),
      ADR3 => g_1_des_one_register_out(0),
      O => g_1_des_one_MUX_BLOCK_N3
    );
  g_1_des_one_n01041111_G : X_LUT3
    generic map(
      INIT => X"20"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1730
    );
  floor_2_2_OBUF : X_BUF
    port map (
      I => g_2_FR_one_state(2),
      O => floor_2_2_OBUF_GTS_TRI
    );
  g_1_des_one_n01001111_G : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => load_enable1,
      ADR1 => g_cu_des_1,
      ADR2 => g_1_FR_one_state(0),
      ADR3 => g_1_FR_one_state(2),
      O => N1732
    );
  g_1_des_one_n00961111_G : X_LUT3
    generic map(
      INIT => X"20"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1734
    );
  g_1_des_one_floor_0_1_SW1 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => g_1_des_one_register_out(2),
      ADR1 => g_1_des_one_register_out(1),
      ADR2 => g_1_des_one_register_out(0),
      O => N1700
    );
  g_1_des_one_n00921111_G : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => load_enable1,
      ADR1 => g_cu_des_1,
      ADR2 => g_1_FR_one_state(0),
      ADR3 => g_1_FR_one_state(2),
      O => N1736
    );
  re_n02824_SW01_G : X_LUT3
    generic map(
      INIT => X"DF"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1738
    );
  g_1_des_one_floor_0_SW0 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => g_1_des_one_register_out(5),
      ADR1 => g_1_FR_one_state(0),
      ADR2 => g_1_des_one_register_out(6),
      ADR3 => N1696,
      O => N1664
    );
  g_cu_n000511 : X_LUT4
    generic map(
      INIT => X"FF02"
    )
    port map (
      ADR0 => re_req_out_1(0),
      ADR1 => g_1_des_one_down,
      ADR2 => re_r_down_1,
      ADR3 => re_req_out_1(1),
      O => CHOICE1322
    );
  g_2_des_one_n01001111_G : X_LUT4
    generic map(
      INIT => X"AAEA"
    )
    port map (
      ADR0 => load_enable2,
      ADR1 => g_cu_des_2,
      ADR2 => g_2_FR_one_state(0),
      ADR3 => g_2_FR_one_state(2),
      O => N1740
    );
  g_1_des_one_register_out_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0009,
      CE => g_1_des_one_n0100,
      RST => g_1_des_one_register_out_3_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(3),
      SET => GND
    );
  g_1_des_one_floor_0_SW0_SW0 : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => g_1_des_one_register_out(4),
      ADR1 => g_1_des_one_register_out(3),
      ADR2 => g_1_des_one_register_out(2),
      O => N1696
    );
  g_1_des_one_n00111 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_2_IBUF,
      O => g_1_des_one_n0011
    );
  g_1_des_one_register_out_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0001,
      CE => g_1_des_one_n0092,
      RST => g_1_des_one_register_out_7_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(7),
      SET => GND
    );
  g_1_des_one_register_out_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0007,
      CE => g_1_des_one_n0098,
      RST => g_1_des_one_register_out_4_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(4),
      SET => GND
    );
  g_1_des_one_register_out_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0003,
      CE => g_1_des_one_n0094,
      RST => g_1_des_one_register_out_6_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(6),
      SET => GND
    );
  g_1_des_one_register_out_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_1_des_one_n0011,
      CE => g_1_des_one_n0102,
      RST => g_1_des_one_register_out_2_GSR_OR,
      CLK => clk_BUFGP,
      O => g_1_des_one_register_out(2),
      SET => GND
    );
  re_n02804_SW01_G : X_LUT3
    generic map(
      INIT => X"DF"
    )
    port map (
      ADR0 => code_0_IBUF,
      ADR1 => code_1_IBUF,
      ADR2 => load_enable_IBUF,
      O => N1742
    );
  g_1_des_one_Mmux_n0016_n0016_n0016_rn_0 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_floor_1_MUXF55,
      IB => g_1_des_one_MUX_BLOCK_floor_1_MUXF54,
      SEL => g_1_FR_one_state(2),
      O => g_1_des_one_MUX_BLOCK_n0018
    );
  g_1_des_one_floor_1_rn_4 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N12,
      IB => g_1_des_one_MUX_BLOCK_N11,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF55
    );
  g_1_des_one_floor_0_11 : X_LUT4
    generic map(
      INIT => X"1011"
    )
    port map (
      ADR0 => g_1_des_one_register_out(3),
      ADR1 => N1682,
      ADR2 => g_1_FR_one_state(0),
      ADR3 => g_1_des_one_register_out(1),
      O => g_1_des_one_MUX_BLOCK_N12
    );
  g_1_des_one_n00151 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      ADR3 => des_req_0_IBUF,
      O => g_1_des_one_n0015
    );
  g_1_des_one_floor_0_Q : X_LUT3
    generic map(
      INIT => X"FE"
    )
    port map (
      ADR0 => g_1_des_one_register_out(1),
      ADR1 => g_1_des_one_register_out(0),
      ADR2 => N1664,
      O => g_1_des_one_MUX_BLOCK_N1
    );
  g_1_des_one_floor_0_1 : X_LUT4
    generic map(
      INIT => X"FFEA"
    )
    port map (
      ADR0 => g_1_des_one_register_out(3),
      ADR1 => g_1_FR_one_state(0),
      ADR2 => g_1_des_one_register_out(4),
      ADR3 => N1700,
      O => g_1_des_one_MUX_BLOCK_N2
    );
  g_1_des_one_floor_1_Q : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N2,
      IB => g_1_des_one_MUX_BLOCK_N1,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF5
    );
  g_1_des_one_floor_0_3 : X_LUT2
    generic map(
      INIT => X"8"
    )
    port map (
      ADR0 => g_1_des_one_register_out(0),
      ADR1 => g_1_FR_one_state(0),
      O => g_1_des_one_MUX_BLOCK_N4
    );
  g_1_des_one_floor_1_rn_0 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_N4,
      IB => g_1_des_one_MUX_BLOCK_N3,
      SEL => g_1_FR_one_state(1),
      O => g_1_des_one_MUX_BLOCK_floor_1_MUXF51
    );
  g_1_des_one_Mmux_n0016_n0016 : X_MUX2
    port map (
      IA => g_1_des_one_MUX_BLOCK_floor_1_MUXF51,
      IB => g_1_des_one_MUX_BLOCK_floor_1_MUXF5,
      SEL => g_1_FR_one_state(2),
      O => g_1_des_one_n0016
    );
  g_1_des_one_floor_0_4 : X_LUT3
    generic map(
      INIT => X"E4"
    )
    port map (
      ADR0 => g_1_FR_one_state(0),
      ADR1 => g_1_des_one_register_out(6),
      ADR2 => g_1_des_one_register_out(7),