g_ele_translate.vhd

电梯控制器 用于八层楼双电梯的协调调度 可进行扩展

  signal CHOICE1464 : STD_LOGIC; 
  signal CHOICE1456 : STD_LOGIC; 
  signal N1608 : STD_LOGIC; 
  signal CHOICE1395 : STD_LOGIC; 
  signal CHOICE1332 : STD_LOGIC; 
  signal CHOICE1484 : STD_LOGIC; 
  signal CHOICE1446 : STD_LOGIC; 
  signal CHOICE1347 : STD_LOGIC; 
  signal CHOICE1644 : STD_LOGIC; 
  signal CHOICE1642 : STD_LOGIC; 
  signal CHOICE1725 : STD_LOGIC; 
  signal N1602 : STD_LOGIC; 
  signal CHOICE1507 : STD_LOGIC; 
  signal CHOICE1551 : STD_LOGIC; 
  signal CHOICE1640 : STD_LOGIC; 
  signal CHOICE1700 : STD_LOGIC; 
  signal N1594 : STD_LOGIC; 
  signal CHOICE1618 : STD_LOGIC; 
  signal N1600 : STD_LOGIC; 
  signal CHOICE1751 : STD_LOGIC; 
  signal CHOICE1666 : STD_LOGIC; 
  signal N1519 : STD_LOGIC; 
  signal CHOICE1577 : STD_LOGIC; 
  signal CHOICE1532 : STD_LOGIC; 
  signal CHOICE1650 : STD_LOGIC; 
  signal CHOICE1565 : STD_LOGIC; 
  signal N1680 : STD_LOGIC; 
  signal CHOICE1513 : STD_LOGIC; 
  signal CHOICE1635 : STD_LOGIC; 
  signal CHOICE1737 : STD_LOGIC; 
  signal CHOICE1687 : STD_LOGIC; 
  signal CHOICE1593 : STD_LOGIC; 
  signal N1574 : STD_LOGIC; 
  signal CHOICE1653 : STD_LOGIC; 
  signal N1537 : STD_LOGIC; 
  signal N1553 : STD_LOGIC; 
  signal CHOICE1536 : STD_LOGIC; 
  signal N1660 : STD_LOGIC; 
  signal CHOICE1797 : STD_LOGIC; 
  signal CHOICE1791 : STD_LOGIC; 
  signal N1531 : STD_LOGIC; 
  signal CHOICE1517 : STD_LOGIC; 
  signal CHOICE1735 : STD_LOGIC; 
  signal CHOICE1614 : STD_LOGIC; 
  signal CHOICE1676 : STD_LOGIC; 
  signal N1591 : STD_LOGIC; 
  signal N1534 : STD_LOGIC; 
  signal N1540 : STD_LOGIC; 
  signal CHOICE1679 : STD_LOGIC; 
  signal N1604 : STD_LOGIC; 
  signal CHOICE1526 : STD_LOGIC; 
  signal CHOICE1581 : STD_LOGIC; 
  signal CHOICE1712 : STD_LOGIC; 
  signal CHOICE1668 : STD_LOGIC; 
  signal N1662 : STD_LOGIC; 
  signal CHOICE1597 : STD_LOGIC; 
  signal N1516 : STD_LOGIC; 
  signal CHOICE1710 : STD_LOGIC; 
  signal CHOICE1661 : STD_LOGIC; 
  signal N1508 : STD_LOGIC; 
  signal N1596 : STD_LOGIC; 
  signal CHOICE1670 : STD_LOGIC; 
  signal g_2_FR_one_state_0_1 : STD_LOGIC; 
  signal g_2_FR_one_state_1_1 : STD_LOGIC; 
  signal g_2_FR_one_state_2_1 : STD_LOGIC; 
  signal g_1_FR_one_state_0_1 : STD_LOGIC; 
  signal N1727 : STD_LOGIC; 
  signal N1728 : STD_LOGIC; 
  signal N1729 : STD_LOGIC; 
  signal N1730 : STD_LOGIC; 
  signal N1731 : STD_LOGIC; 
  signal N1732 : STD_LOGIC; 
  signal N1733 : STD_LOGIC; 
  signal N1734 : STD_LOGIC; 
  signal N1735 : STD_LOGIC; 
  signal N1736 : STD_LOGIC; 
  signal N1737 : STD_LOGIC; 
  signal N1738 : STD_LOGIC; 
  signal N1739 : STD_LOGIC; 
  signal N1740 : STD_LOGIC; 
  signal N1741 : STD_LOGIC; 
  signal N1742 : STD_LOGIC; 
  signal N1743 : STD_LOGIC; 
  signal N1744 : STD_LOGIC; 
  signal N1745 : STD_LOGIC; 
  signal N1746 : STD_LOGIC; 
  signal N1747 : STD_LOGIC; 
  signal N1748 : STD_LOGIC; 
  signal N1749 : STD_LOGIC; 
  signal N1750 : STD_LOGIC; 
  signal N1751 : STD_LOGIC; 
  signal N1752 : STD_LOGIC; 
  signal N1753 : STD_LOGIC; 
  signal N1754 : STD_LOGIC; 
  signal N1755 : STD_LOGIC; 
  signal N1756 : STD_LOGIC; 
  signal N1757 : STD_LOGIC; 
  signal N1758 : STD_LOGIC; 
  signal N1759 : STD_LOGIC; 
  signal N1760 : STD_LOGIC; 
  signal N1761 : STD_LOGIC; 
  signal N1762 : STD_LOGIC; 
  signal N1763 : STD_LOGIC; 
  signal N1764 : STD_LOGIC; 
  signal N1765 : STD_LOGIC; 
  signal N1767 : STD_LOGIC; 
  signal N1768 : STD_LOGIC; 
  signal N1769 : STD_LOGIC; 
  signal N1770 : STD_LOGIC; 
  signal N1771 : STD_LOGIC; 
  signal N1772 : STD_LOGIC; 
  signal N1773 : STD_LOGIC; 
  signal N1774 : STD_LOGIC; 
  signal N1775 : STD_LOGIC; 
  signal N1776 : STD_LOGIC; 
  signal N1777 : STD_LOGIC; 
  signal N1778 : STD_LOGIC; 
  signal N1779 : STD_LOGIC; 
  signal N1780 : STD_LOGIC; 
  signal g_1_des_one_register_out_7_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_6_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_5_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_4_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_3_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_2_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_1_1 : STD_LOGIC; 
  signal g_1_des_one_register_out_0_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_7_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_6_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_5_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_4_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_3_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_2_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_1_1 : STD_LOGIC; 
  signal g_2_des_one_register_out_0_1 : STD_LOGIC; 
  signal g_1_cu_one_Ker046_F_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_3_23_SW0_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_2_13_SW0_O : STD_LOGIC; 
  signal g_2_cu_one_Ker81_SW1_O : STD_LOGIC; 
  signal g_2_cu_one_Ker046_G_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_3_23_SW0_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_2_13_SW0_O : STD_LOGIC; 
  signal g_1_cu_one_Ker81_SW1_O : STD_LOGIC; 
  signal re_n02664_SW11_G_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_1_SW0_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_2_90_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_1_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_0_86_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_2_69_O : STD_LOGIC; 
  signal g_2_cu_one_FLE1_O : STD_LOGIC; 
  signal re_n028022_SW0_O : STD_LOGIC; 
  signal re_n02664_SW0_O : STD_LOGIC; 
  signal re_n02724_SW0_O : STD_LOGIC; 
  signal re_n02684_SW0_O : STD_LOGIC; 
  signal re_n027818_SW0_O : STD_LOGIC; 
  signal g_1_cu_one_Ker151_SW4_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_1_46_O : STD_LOGIC; 
  signal g_1_cu_one_FLE1_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_2_90_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_1_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_0_86_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_0_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_0_O : STD_LOGIC; 
  signal re_n028222_SW0_O : STD_LOGIC; 
  signal g_2_cu_one_Ker151_SW4_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_1_46_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_3_30_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_1_SW0_O : STD_LOGIC; 
  signal re_n02924_SW0_SW0_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_2_76_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_2_48_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_3_30_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_2_5_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_3_18_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_3_20_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_2_76_O : STD_LOGIC; 
  signal re_n02764_SW0_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_2_5_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_0_69_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_2_69_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_1_34_G_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_0_24_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_3_18_O : STD_LOGIC; 
  signal g_1_cu_one_n0000_0_69_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_3_20_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_1_34_G_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_2_48_O : STD_LOGIC; 
  signal g_2_cu_one_n0000_0_24_O : STD_LOGIC; 
  signal g_1_cu_one_Ker046_G_O : STD_LOGIC; 
  signal re_n02824_SW01_F_O : STD_LOGIC; 
  signal re_n02804_SW01_F_O : STD_LOGIC; 
  signal g_2_cu_one_Ker046_F_O : STD_LOGIC; 
  signal re_n02844_SW01_F_O : STD_LOGIC; 
  signal re_n02904_SW01_F_O : STD_LOGIC; 
  signal re_n02884_SW01_F_O : STD_LOGIC; 
  signal re_n02864_SW01_F_O : STD_LOGIC; 
  signal g_2_cu_one_n0001_1_34_F_O : STD_LOGIC; 
  signal g_1_cu_one_n0001_1_34_F_O : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal g_2_cu_one_temp_1_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_2_GSR_OR : STD_LOGIC; 
  signal g_2_lamp_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_1_FR_one_state_2_GSR_OR : STD_LOGIC; 
  signal g_2_lamp_one_state_1_GSR_OR : STD_LOGIC; 
  signal pv_two_pv_out_GSR_OR : STD_LOGIC; 
  signal pv_one_pv_out_GSR_OR : STD_LOGIC; 
  signal g_1_lamp_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_1_lamp_one_state_1_GSR_OR : STD_LOGIC; 
  signal g_1_FR_one_state_1_GSR_OR : STD_LOGIC; 
  signal g_1_FR_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_1_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_5_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_0_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_3_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_7_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_4_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_6_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_2_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_5_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_0_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_3_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_7_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_4_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_6_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_2_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_temp_2_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_state_3_GSR_OR : STD_LOGIC; 
  signal re_register_2_0_GSR_OR : STD_LOGIC; 
  signal re_register_6_1_GSR_OR : STD_LOGIC; 
  signal re_register_2_1_GSR_OR : STD_LOGIC; 
  signal re_register_6_0_GSR_OR : STD_LOGIC; 
  signal re_register_7_1_GSR_OR : STD_LOGIC; 
  signal re_register_5_1_GSR_OR : STD_LOGIC; 
  signal re_register_3_1_GSR_OR : STD_LOGIC; 
  signal re_register_4_1_GSR_OR : STD_LOGIC; 
  signal re_register_0_0_GSR_OR : STD_LOGIC; 
  signal re_register_1_1_GSR_OR : STD_LOGIC; 
  signal re_register_4_0_GSR_OR : STD_LOGIC; 
  signal re_register_1_0_GSR_OR : STD_LOGIC; 
  signal re_register_5_0_GSR_OR : STD_LOGIC; 
  signal re_register_3_0_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_temp_3_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_state_2_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_temp_2_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_state_3_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_temp_1_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_temp_0_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_state_1_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_1_cu_one_state_2_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_state_0_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_state_1_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_temp_0_GSR_OR : STD_LOGIC; 
  signal g_2_cu_one_temp_3_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_0_1_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_1_1_GSR_OR : STD_LOGIC; 
  signal g_2_FR_one_state_2_1_GSR_OR : STD_LOGIC; 
  signal g_1_FR_one_state_0_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_7_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_6_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_5_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_4_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_3_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_2_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_1_1_GSR_OR : STD_LOGIC; 
  signal g_1_des_one_register_out_0_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_7_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_6_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_5_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_4_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_3_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_2_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_1_1_GSR_OR : STD_LOGIC; 
  signal g_2_des_one_register_out_0_1_GSR_OR : STD_LOGIC; 
  signal d_floor_1_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal d_floor_1_7_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_1_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_1_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_2_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_2_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_1_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal run_state_1_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_7_OBUF_GTS_TRI : STD_LOGIC; 
  signal floor_2_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_6_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal run_state_2_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal run_state_2_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal run_state_1_0_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_1_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_3_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_4_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_2_2_OBUF_GTS_TRI : STD_LOGIC; 
  signal d_floor_1_5_OBUF_GTS_TRI : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_7_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_1_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_1_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_2_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_2_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_1_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_run_state_1_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_7_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_floor_2_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_6_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_run_state_2_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_run_state_2_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_run_state_1_0_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_1_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_3_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_4_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_2_2_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal NlwInverterSignal_d_floor_1_5_OBUF_GTS_TRI_CTL : STD_LOGIC; 
  signal g_cu_req_clr_2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_cu_mov_1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_cu_req_clr_1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_cu_mov_2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_2_lamp_one_state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_2_des_one_register_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal re_req_out_2 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal re_req_out_1 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_1_lamp_one_state : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_1_FR_one_state : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal g_2_FR_one_state : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal g_1_des_one_register_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal g_1_lamp_one_n0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_2_lamp_one_n0000 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_1_FR_one_n0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal g_2_FR_one_n0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal g_2_cu_one_n0001 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_2_cu_one_n0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_2_cu_one_state : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_cu_MUX_BLOCK_n0004 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_2_cu_one_temp : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_cu_MUX_BLOCK_n0008 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal g_cu_n0096 : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal g_cu_n0083 : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal re_MUX_BLOCK_n0037 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal re_n0034 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal re_n0037 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal re_MUX_BLOCK_n0034 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal g_1_cu_one_n0001 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_1_cu_one_n0000 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_1_cu_one_temp : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal g_1_cu_one_state : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  g_1_lamp_one_n0000_0_1 : X_LUT3
    generic map(
      INIT => X"C4"
    )
    port map (
      ADR0 => g_cu_mov_1(1),
      ADR1 => g_cu_mov_1(0),
      ADR2 => g_1_lamp_one_state(0),
      O => g_1_lamp_one_n0000(0)
    );
  g_2_lamp_one_n0000_0_1 : X_LUT3
    generic map(
      INIT => X"C4"
    )
    port map (
      ADR0 => g_cu_mov_2(1),
      ADR1 => g_cu_mov_2(0),
      ADR2 => g_2_lamp_one_state(0),
      O => g_2_lamp_one_n0000(0)
    );
  g_2_lamp_one_n0000_1_1 : X_LUT3
    generic map(
      INIT => X"C4"
    )
    port map (
      ADR0 => g_cu_mov_2(0),
      ADR1 => g_cu_mov_2(1),
      ADR2 => g_2_lamp_one_state(1),
      O => g_2_lamp_one_n0000(1)
    );
  re_n028222 : X_LUT4
    generic map(
      INIT => X"331B"
    )
    port map (
      ADR0 => g_2_FR_one_state_2_1,
      ADR1 => N1553,
      ADR2 => N1557,
      ADR3 => N1602,
      O => re_n0282
    );
  LE_encoder_m2_out1 : X_LUT3
    generic map(
      INIT => X"20"
    )
    port map (
      ADR0 => code_1_IBUF,
      ADR1 => code_0_IBUF,
      ADR2 => load_enable_IBUF,
      O => load_enable1
    );
  g_2_cu_one_temp_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => g_2_cu_one_n0001(1),
      RST => g_2_cu_one_temp_1_GSR_OR,
      CLK => Q_n0009,
      O => g_2_cu_one_temp(1),
      CE => VCC,
      SET => GND
    );
  g_1_total_one_n00011 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => g_1_des_one_down,
      ADR1 => re_r_down_1,
      O => down_1
    );
  g_2_total_one_n00011 : X_LUT2
    generic map(
      INIT => X"E"
    )
    port map (
      ADR0 => g_2_des_one_down,
      ADR1 => re_r_down_2,
      O => down_2