📄 g_eletest.v
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`timescale 1ns/1psmodule test; reg clk,reset,re_in,open_1,open_2,close_1,close_2,load_enable; reg [7:0] des_req; reg [1:0] code; wire [1:0] state1,state2; wire [2:0] floor_1,floor_2; wire [7:0] d1,d2; always #50 clk = ~clk; initial begin clk = 0; reset = 1; re_in = 0; open_1 =0; open_2 = 0; close_1 = 0; close_2 = 0; load_enable = 0; des_req = 8'b0000_0000; code = 2'b00; #400 reset = 0; #230 reset = 1; //######################### #300 re_in = 1; #100 des_req = 8'b0000_0100; code = 2'b00; load_enable = 1;
#100 des_req = 8'b1001_0001; code = 2'b01; load_enable = 1;
#100 des_req = 8'b1010_1110; code = 2'b10; load_enable = 1;
#100 des_req = 8'b01001110; code = 2'b11; load_enable = 1; #100 load_enable = 0; #100 re_in = 0; #20000 $stop; end g_ele uut(.clk(clk),.reset(reset),.re_in(re_in),. des_req(des_req),.code(code), .open_1(open_1),.open_2(open_2),.close_1(close_1),.close_2(close_2), .load_enable(load_enable),.floor_1(floor_1),.floor_2(floor_2), .run_state_1(state1),.run_state_2(state2),.d_floor_1(d1),.d_floor_2(d2));endmodule
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