📄 totaltest.v
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:29 01/26/2007
// Design Name: total_des
// Module Name: totaltest.v
// Project Name: lift
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: total_des
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module totaltest_v;
// Inputs
reg req_up;
reg req_down;
reg des_up;
reg des_down;
// Outputs
wire up;
wire down;
// Instantiate the Unit Under Test (UUT)
total_des uut (
.req_up(req_up),
.req_down(req_down),
.des_up(des_up),
.des_down(des_down),
.up(up),
.down(down)
);
initial begin
// Initialize Inputs
req_up = 0;
req_down = 0;
des_up = 0;
des_down = 0;
// Wait 100 ns for global reset to finish
#100;
req_up = 1;
# 200
des_down = 1;
# 200
req_up = 0;
des_up = 1;
# 250
req_down = 1;
des_down = 0;
// Add stimulus here
# 300 $stop;
end
endmodule
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