📄 l_cutest.v
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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:43:40 01/26/2007
// Design Name: l_cu
// Module Name: l_cutest.v
// Project Name: lift
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: l_cu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module l_cutest_v;
// Inputs
reg clk_i;
reg rst_i;
reg re_in;
reg open;
reg close;
reg [2:0] floor;
reg stop;
reg pv_in;
// Outputs
wire oopen;
wire cclose;
wire clear;
wire move;
wire FLE;
wire request;
wire call;
wire pv_out;
wire le;
// Instantiate the Unit Under Test (UUT)
l_cu uut (
.clk_i(clk_i),
.rst_i(rst_i),
.re_in(re_in),
.open(open),
.close(close),
.floor(floor),
.stop(stop),
.oopen(oopen),
.cclose(cclose),
.clear(clear),
.move(move),
.FLE(FLE),
.request(request),
.call(call),
.pv_in(pv_in),
.pv_out(pv_out),
.le(le)
);
wire [3:0] state ;
assign state = uut.state;
initial begin
// Initialize Inputs
clk_i = 0;
rst_i = 0;
re_in = 0;
open = 0;
close = 0;
floor = 0;
stop = 0;
pv_in = 0;
// Wait 100 ns for global reset to finish
#100;
rst_i = 1;
# 50;
# 200 floor = 1;
# 1000;
stop = 1;
#50 re_in = 1;
# 2000 re_in = 0;
# 4000;
$stop;
// Add stimulus here
end
always # 100 clk_i = ~clk_i;
endmodule
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