requesttest.v

电梯控制器 用于八层楼双电梯的协调调度 可进行扩展

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:50:14 01/26/2007
// Design Name:   request
// Module Name:   requesttest.v
// Project Name:  lift
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: request
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module requesttest_v;

	// Inputs
	reg clk;
	reg reset;
	reg drive_1;
	reg drive_2;
	reg load_enable_low;
	reg load_enable_high;
	reg [2:0] floor_1;
	reg [2:0] floor_2;
	reg [1:0] req_clr_1;
	reg [1:0] req_clr_2;
	reg [1:0] req_in_0;
	reg [1:0] req_in_1;
	reg [1:0] req_in_2;
	reg [1:0] req_in_3;
	reg [1:0] req_in_4;
	reg [1:0] req_in_5;
	reg [1:0] req_in_6;
	reg [1:0] req_in_7;

	// Outputs
	wire [1:0] req_out_1;
	wire [1:0] req_out_2;
	wire r_up_1;
	wire r_up_2;
	wire r_down_1;
	wire r_down_2;

	// Instantiate the Unit Under Test (UUT)
	request uut (
		.clk(clk), 
		.reset(reset), 
		.drive_1(drive_1), 
		.drive_2(drive_2), 
		.load_enable_low(load_enable_low), 
		.load_enable_high(load_enable_high), 
		.floor_1(floor_1), 
		.floor_2(floor_2), 
		.req_clr_1(req_clr_1), 
		.req_clr_2(req_clr_2), 
		.req_in_0(req_in_0), 
		.req_in_1(req_in_1), 
		.req_in_2(req_in_2), 
		.req_in_3(req_in_3), 
		.req_in_4(req_in_4), 
		.req_in_5(req_in_5), 
		.req_in_6(req_in_6), 
		.req_in_7(req_in_7), 
		.req_out_1(req_out_1), 
		.req_out_2(req_out_2), 
		.r_up_1(r_up_1), 
		.r_up_2(r_up_2), 
		.r_down_1(r_down_1), 
		.r_down_2(r_down_2)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		drive_1 = 0;
		drive_2 = 0;
		load_enable_low = 0;
		load_enable_high = 0;
		floor_1 = 0;
		floor_2 = 0;
		req_clr_1 = 0;
		req_clr_2 = 0;
		req_in_0 = 0;
		req_in_1 = 0;
		req_in_2 = 0;
		req_in_3 = 0;
		req_in_4 = 0;
		req_in_5 = 0;
		req_in_6 = 0;
		req_in_7 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule