lcd计数显示程序.txt

利用VHDL语言编写,在lcd上显示计数.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( clk : in std_logic;
			  resetn : in std_logic;
           dout : out std_logic_vector(7 downto 0);
           lcd_en : out std_logic;
           lcd_rs : out std_logic;
           lcd_rw   : out std_logic);
end counter;

architecture Behavioral of counter is

component counter60 is
	Port ( clk : in std_logic;
         resetn : in std_logic;
         dout : out std_logic_vector(7 downto 0));
end component;

component decoder is
  Port (din:in std_logic_vector(3 downto 0 );   
        dout:out std_logic_vector(8 downto 0) ); 
end component;


component  lcd_interface  is
	 port (
            clk                 : in std_logic;
            resetn              : in std_logic;
				dout_s10				  : in std_logic_vector (8 downto 0);
				dout_s1				  : in std_logic_vector (8 downto 0);
            lcd_data            : out std_logic_vector (7 downto 0);
            lcd_en              : out std_logic;
            lcd_rs              : out std_logic;
            lcd_rw              : out std_logic
				
           );


end component;

 signal 	ddout_s10 : std_logic_vector (8 downto 0);
 signal 	ddout_s1  : std_logic_vector (8 downto 0);
 signal 	ddout  : std_logic_vector (7downto 0);

begin
	
	u1: counter60 port map(clk,resetn,ddout);
	u2: decoder	  port map(ddout(7 downto 4),ddout_s10);
   u3: decoder	  port map(ddout(3 downto 0),ddout_s1);
	u4: lcd_interface	 port map(clk,resetn, ddout_s10,ddout_s1,dout,lcd_en,  lcd_rs , lcd_rw);





end Behavioral;













--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    13:36:10 03/30/06
-- Design Name:    
-- Module Name:    count60 - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter60 is
    Port ( clk : in std_logic;
         resetn : in std_logic;
         dout : out std_logic_vector(7 downto 0));
end counter60;
architecture Behavioral of counter60 is

signal count : std_logic_vector(7 downto 0);
signal count_div  : std_logic_vector (25 downto 0);

begin
    
	 dout <= count;

	 		process (clk)
  begin
    if (clk'event and clk = '1') then
        if (resetn = '0')  then
            count_div  <= (others => '0');
			
        else if (count_div (25) = '1') then 
		
			count_div  <= (others =>'0')	;
			else
           count_div <= count_div  + 1;
        end if;
    end if;
	 end if;
  end process;


	process(clk ,resetn)
	begin
	   if resetn= '0' then
		   count <= (others => '0'); 
       elsif rising_edge(clk) then	 
		 if (count_div (25) = '1') then  
		   if count(3 downto 0)="1001" then

			 count(3 downto 0)<="0000";
			count(7 downto 4)<=count(7 downto 4) +1;
         else
			count(3 downto 0)<=count(3 downto 0)+1;
         end if;
		 if count="01011001" then
		   count<="00000000";
         end if;
			 end if;
      end if;
   end process;



end Behavioral;















--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    13:25:37 03/30/06
-- Design Name:    
-- Module Name:    decoder - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (din:in std_logic_vector(3 downto 0 );   --四位二进制码输入
dout:out std_logic_vector(8 downto 0) );  --输出LED七段码
end decoder;
architecture Behavioral of decoder is
begin
process(din)
begin
case din is
when "0000" => dout<="100110000";--30
when "0001" => dout<="100110001";--31
when "0010" => dout<="100110010";--32
when "0011" => dout<="100110011";--33
when "0100" => dout<="100110100"; --34
when "0101" => dout<="100110101";--35
when "0110" => dout<="100110110";--36
when "0111" => dout<="100110111";--37
when "1000" => dout<="100111000";--38
when "1001" => dout<="100111001";--39

when others => dout<="100100000"	;
end case;
end process;
end Behavioral;









library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



entity lcd_interface is
    port (
            clk                 : in std_logic;
            resetn              : in std_logic;
				dout_s10				  : in std_logic_vector (8 downto 0);
				dout_s1				  : in std_logic_vector (8 downto 0);
            lcd_data            : out std_logic_vector (7 downto 0);
            lcd_en              : out std_logic;
            lcd_rs              : out std_logic;
            lcd_rw              : out std_logic
				
           );
end lcd_interface;




architecture lcd_interface_arch of lcd_interface is

signal  lcd_we_n            : std_logic;
signal  lcd_en_int          : std_logic;
signal  w_comp_n            : std_logic;
signal  seq_count           : std_logic_vector (5 downto 0);
signal  lcd_rs_data         : std_logic_vector (8 downto 0);
signal  delay_count         : std_logic_vector (15 downto 0);
signal  lcd_addr            : std_logic_vector (5 downto 0);



type state_lcd_write_type is (lcd_write_idle, lcd_write_1, lcd_write_2, lcd_write_3, lcd_write_4);
signal state_lcd_write : state_lcd_write_type;

type state_type is (idle, wait_1, wait_2, state_1, state_2, state_3, done);
signal state : state_type;

  


begin


--  The following state machine initializes the LCD and writes the following message 
--  to the LCD panel
--                                          Memec Design
--                                          MB1000 Board
--
--
--  The LCD initialization sequence consist of writing the 0x38, 0x38, 0x06, 0x0e,
--  0x01, 0x80, 0xc0 sequence of hex numbers to the LCD control registers (please
--  refer to the LCD datasheet for an explanation of the initialization sequence).
--  At the end of the LCD initialization sequence, the LCD is ready to be written
--  to starting with line 1. It should be noted that delays are inserted between
-- 2 writes to the LCD panel to meet the LCD initialization requirements. Although,
--  the LCD panel requires different delays between 2 writes, a fix delay of 20ms is
--  inserted between 2 writes to simply the initialization design (the 20ms is the
--  longest delay that is required by the LCD panel). A 22-bit counter is used to
--  generate this fix delay.

        sequencer_state_register: process (clk, resetn)

                        begin
                            if (resetn = '0') then
                                state <= idle;
                            elsif (clk'event and clk = '1') then
                                case state is

                                    when idle=>
                                        if (delay_count(15) = '1') then