rpt_vr_fifo.areasrr
来自「可预取的fifo 的fpga 设计代码」· AREASRR 代码 · 共 55 行
AREASRR
55 行
#### START OF AREA REPORT #####[
Part: XC3S500EFT256-4 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: vr_fifo ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 34 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block vr_fifo: 34 (28.57 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 40 100 %
MUXCY 6 100 %
XORCY 6 100 %
MULT18x18/MULT18x18S 0 0.0 %
=================================================================
Total COMBINATIONAL LOGIC in the block vr_fifo: 52 (43.70 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Number of bits Utilization Notes
-------------------------------------------------------------------------
SYNC RAMS 0 0 0.0 %
ROMS 0 0 0.0 %
=========================================================================
Total MEMORY ELEMENTS in the block vr_fifo: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 22 100 %
=================================================
Total IO PADS in the block vr_fifo: 22 (18.49 % Utilization)
##### END OF AREA REPORT #####]
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?