vr_fifo.par

来自「可预取的fifo 的fpga 设计代码」· PAR 代码 · 共 197 行

Release 8.1.03i par I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

WINDY::  Fri Jul 28 23:43:35 2006

par -w -intstyle ise -ol std -t 1 vr_fifo_map.ncd vr_fifo.ncd vr_fifo.pcf 


Constraints file: vr_fifo.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment D:\Xilinx.
   "vr_fifo" is an NCD, version 3.1, device xc3s500e, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.21 2006-03-12".


Design Summary Report:

 Number of External IOBs                          22 out of 190    11%

   Number of External Input IOBs                 12

      Number of External Input IBUFs             12

   Number of External Output IOBs                10

      Number of External Output IOBs             10

   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                  1 out of 24      4%
   Number of Slices                   35 out of 4656    1%
      Number of SLICEMs                8 out of 2328    1%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9897cf) REAL time: 5 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs 

Phase 3.2
......
..


Phase 3.2 (Checksum:1c9c37d) REAL time: 10 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 10 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 10 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 10 secs 

Phase 7.8
..............
...........
.................
.......................
..................
Phase 7.8 (Checksum:9b004d) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 11 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 11 secs 

Writing design to file vr_fifo.ncd


Total REAL time to Placer completion: 11 secs 
Total CPU time to Placer completion: 11 secs 

Starting Router

Phase 1: 279 unrouted;       REAL time: 16 secs 

Phase 2: 249 unrouted;       REAL time: 16 secs 

Phase 3: 59 unrouted;       REAL time: 16 secs 

Phase 4: 59 unrouted; (1293)      REAL time: 16 secs 

Phase 5: 57 unrouted; (358)      REAL time: 16 secs 

Phase 6: 60 unrouted; (230)      REAL time: 16 secs 

Phase 7: 0 unrouted; (168)      REAL time: 17 secs 

Phase 8: 0 unrouted; (168)      REAL time: 17 secs 

Phase 9: 0 unrouted; (108)      REAL time: 17 secs 

Phase 10: 0 unrouted; (0)      REAL time: 19 secs 

Phase 11: 0 unrouted; (0)      REAL time: 19 secs 

WARNING:Route:447 - CLK Net:clk_c may have excessive skew because 
   26 CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 19 secs 
Total CPU time to Router completion: 19 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|               clk_c | BUFGMUX_X2Y10| No   |   29 |  0.015     |  0.175      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.091
   The MAXIMUM PIN DELAY IS:                               4.501
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.701

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         152          95          19           6           4           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of  
                                            |            |            | Levels | Slack      |errors     
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 5.1 ns HIGH | 5.100ns    | 4.941ns    | 2      | 0.159ns    | 0         
   50%                                      |            |            |        |            |           
------------------------------------------------------------------------------------------------------


All constraints were met.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 22 secs 
Total CPU time to PAR completion: 21 secs 

Peak Memory Usage:  170 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0

Writing design to file vr_fifo.ncd



PAR done!