vr_fifo.ncf

可预取的fifo 的fpga 设计代码

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "fifo_full_rep0_i" IOB=FALSE;
INST "out_dat[7]" IOB=FALSE;
INST "out_dat[6]" IOB=FALSE;
INST "out_dat[5]" IOB=FALSE;
INST "out_dat[4]" IOB=FALSE;
INST "out_dat[3]" IOB=FALSE;
INST "out_dat[2]" IOB=FALSE;
INST "out_dat[1]" IOB=FALSE;
INST "out_dat[0]" IOB=FALSE;

# Location Constraints

# End of generated constraints