vr_fifo.edn

可预取的fifo 的fpga 设计代码

(edif vr_fifo
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 7 28 23 43 15)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell RAM16X1D (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DPO (direction OUTPUT))
           (port SPO (direction OUTPUT))
           (port A0 (direction INPUT))
           (port A1 (direction INPUT))
           (port A2 (direction INPUT))
           (port A3 (direction INPUT))
           (port D (direction INPUT))
           (port DPRA0 (direction INPUT))
           (port DPRA1 (direction INPUT))
           (port DPRA2 (direction INPUT))
           (port DPRA3 (direction INPUT))
           (port WCLK (direction INPUT)
 )
           (port WE (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT4_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT1_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell XORCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port LI (direction INPUT))
           (port CI (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXCY_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDPE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell vr_fifo (cellType GENERIC)
       (view rtl (viewType NETLIST)
         (interface
           (port (array (rename in_dat "in_dat(7:0)") 8) (direction INPUT))
           (port (array (rename out_dat "out_dat(7:0)") 8) (direction OUTPUT))
           (port rst_n (direction INPUT)
 )
           (port clk (direction INPUT)
 )
           (port in_vld (direction INPUT)
 )
           (port in_rdy (direction OUTPUT))
           (port out_vld (direction OUTPUT))
           (port out_rdy (direction INPUT)
 )
         )
         (contents
          (instance (rename proc_fifo_status_un8_fifo_we_axb_0 "proc_fifo_status.un8_fifo_we_axb_0") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance (rename proc_fifo_status_un8_fifo_we_axb_1 "proc_fifo_status.un8_fifo_we_axb_1") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance (rename proc_fifo_status_un8_fifo_we_axb_2 "proc_fifo_status.un8_fifo_we_axb_2") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance (rename proc_fifo_status_un22_fifo_re_axb_0 "proc_fifo_status.un22_fifo_re_axb_0") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance (rename proc_fifo_status_un22_fifo_re_axb_1 "proc_fifo_status.un22_fifo_re_axb_1") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance (rename proc_fifo_status_un22_fifo_re_axb_2 "proc_fifo_status.un22_fifo_re_axb_2") (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance fifo_empty (viewRef PRIM (cellRef FDPE (libraryRef UNILIB)))
          )
          (instance fifo_full (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_0 "out_dat[0]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_1 "out_dat[1]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_2 "out_dat[2]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_3 "out_dat[3]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_4 "out_dat[4]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_5 "out_dat[5]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )
          (instance (rename out_datZ0Z_6 "out_dat[6]") (viewRef PRIM (cellRef FDCE (libraryRef UNILIB)))
          )