vr_fifo.twr

可预取的fifo 的fpga 设计代码

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Release 8.1.03i Trace I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:\Xilinx\bin\nt\trce.exe -ise vr_fifo.ise -intstyle ise -e 3 -l 3 -s 4 -xml
vr_fifo vr_fifo.ncd -o vr_fifo.twr vr_fifo.pcf


Design file:              vr_fifo.ncd
Physical constraint file: vr_fifo.pcf
Device,speed:             xc3s500e,-4 (PRODUCTION 1.21 2006-03-12)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5.1 ns HIGH 50%;

 336 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   4.941ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.941|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 336 paths, 0 nets, and 245 connections

Design statistics:
   Minimum period:   4.941ns (Maximum frequency: 202.388MHz)


Analysis completed Fri Jul 28 23:44:04 2006
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Peak Memory Usage: 127 MB