traplog.tlg

来自「可预取的fifo 的fpga 设计代码」· TLG 代码 · 共 16 行

@N:".\gentmp0a02552":4:7:4:9|Synthesizing work.top.gen 
@N:"syng0a02552":123:7:123:13|Synthesizing work.ram_r_w.select_ram 
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@N:"D:\synplicity\fpga_81\lib\xilinx\unisim.vhd":15864:10:15864:17|Synthesizing unisim.ram16x1d.syn_black_box 
Post processing for unisim.ram16x1d.syn_black_box
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
@W: CD326 :"syng0a02552":1836:12:1836:15|Port spo of entity unisim.ram16x1d is unconnected
Post processing for work.ram_r_w.select_ram
@W: CL159 :"syng0a02552":141:2:141:5|Input oclk is unused
Post processing for work.top.gen