vr_fifo.plg

来自「可预取的fifo 的fpga 设计代码」· PLG 代码 · 共 13 行

@P:  Worst Slack : 993.353
@P:  vr_fifo|clk - Estimated Frequency : 150.4 MHz
@P:  vr_fifo|clk - Requested Frequency : 1.0 MHz
@P:  vr_fifo|clk - Estimated Period : 6.647
@P:  vr_fifo|clk - Requested Period : 1000.000
@P:  vr_fifo|clk - Slack : 993.353
@P: vr_fifo Part : xc3s500eft256-4
@P: vr_fifo I/O primitives : 21
@P: vr_fifo I/O Register bits : 0
@P: vr_fifo Register bits (Non I/O) : 34 (0%)
@P: vr_fifo Dual Port Rams (RAM16X1D) : 8
@P: vr_fifo Total Luts : 56 (0%)