vr_fifo_srr.htm

可预取的fifo 的fpga 设计代码

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VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

@N: : <a href="e:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd:15:7:15:14:@N::@XP_MSG">vr_fifo_rtl.vhd(15)</a><!@TM:1154101393> | Synthesizing work.vr_fifo.rtl 
Post processing for work.vr_fifo.rtl
@N:<a href="@N:CL134:@XP_HELP">CL134</a> : <a href="e:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd:41:9:41:17:@N:CL134:@XP_MSG">vr_fifo_rtl.vhd(41)</a><!@TM:1154101393> | Found RAM fifo_ary, depth=16, width=8
# Fri Jul 28 23:43:13 2006

Synplicity Netlist Filter, version 3.1.0, Build 044R, built Apr 27 2005
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 28 23:43:13 2006

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 28 23:43:13 2006

###########################################################[
Version 8.1
<a name=mapperReport2>Synplicity Xilinx Technology Mapper, Version 8.1.0, Build 540R, Built May  9 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Reading constraint file: E:\modelsim\vr_fifo\par\vr_fifo.sdc
Reading Xilinx I/O pad type table from file &ltD:\synplicity\fpga_81\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file &ltD:\synplicity\fpga_81\lib/xilinx/gttype.txt> 


RTL optimization done.

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.vr_fifo(rtl):
No nets needed buffering.

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1154101395> | The option to pack flops in the IOB has not been specified  
Writing Analyst data base E:\modelsim\vr_fifo\par\vr_fifo.srm
Writing EDIF Netlist and constraint files
Found clock vr_fifo|clk with period 1000.00ns 


<a name=timingReport3>##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jul 28 23:43:15 2006
#


Top view:               vr_fifo
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    E:\modelsim\vr_fifo\par\vr_fifo.sdc
                       
@N:<a href="@N:MT195:@XP_HELP">MT195</a> : <!@TM:1154101395> | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. 

@N:<a href="@N:MT197:@XP_HELP">MT197</a> : <!@TM:1154101395> | Clock constraints cover only FF-to-FF paths associated with the clock.. 



<a name=performanceSummary4>Performance Summary 
*******************


Worst slack in design: 993.353

                   Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group              
-----------------------------------------------------------------------------------------------------------------------
vr_fifo|clk        1.0 MHz       150.4 MHz     1000.000      6.647         993.353     inferred     Inferred_clkgroup_0
=======================================================================================================================





<a name=clockRelationships5>Clock Relationships
*******************

Clocks                    |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------
Starting     Ending       |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------
vr_fifo|clk  vr_fifo|clk  |  1000.000    993.353  |  No paths    -      |  No paths    -      |  No paths    -    
==================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo6>Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
<a name=resourceUsage7>Resource Usage Report for vr_fifo 

Mapping to part: xc3s500eft256-4
Cell usage:
FDC             13 uses
FDCE            19 uses
FDPE            2 uses
MUXCY_L         6 uses
VCC             1 use
XORCY           6 uses
LUT1            3 uses
LUT2            14 uses
LUT3            15 uses
LUT4            8 uses

I/O primitives: 21
IBUF           11 uses
OBUF           10 uses

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   34 (0%)

RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 8


Global Clock Buffers: 1 of 24 (4%)


Mapping Summary:
Total  LUTs: 56 (0%)

Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
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