_verilog_hintfile

可预取的fifo 的fpga 设计代码

#OPTIONS:"|-bldtbl|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-autosm|-fid2|-sharing|on|-encrypt|-ui|-lite|-pro|-ram|-ignore_undefined_lib|-ll|2000|-lib|work"
#CUR:"D:\\synplicity\\fpga_81\\bin\\c_vhdl.exe":1115125640
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\location.map":1114701536
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std.vhd":1111509844
#CUR:"E:\\modelsim\\vr_fifo\\src\\vr_fifo_rtl.vhd":1154101091
#CUR:"E:\\modelsim\\vr_fifo\\src\\vr_fifo_rtl.vhd":1154101091
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\std1164.vhd":927285456
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\arith.vhd":1035356678
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\unsigned.vhd":1068614572
#CUR:"D:\\synplicity\\fpga_81\\lib\\vhd\\unsigned.vhd":1068614572
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