vr_fifo_rtl.vhd

可预取的fifo 的fpga 设计代码

--
-- VHDL Architecture common_lib.vr_fifo.rtl
--
-- Created:
--          by - Yihua.Zhang.UNKNOWN (CV0009649D2)
--          at - 09:22:44 2006-06-26
--
-- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY vr_fifo IS
   GENERIC( 
      ADR_WIDTH : integer := 4;
      DAT_WIDTH : integer := 8
   );
   PORT( 
      rst_n    : IN     std_logic;
      clk      : IN     std_logic;
      
      in_vld   : IN     std_logic;
      in_rdy   : OUT    std_logic;
      in_dat   : IN     std_logic_vector (DAT_WIDTH-1 DOWNTO 0);
      
      out_vld  : OUT    std_logic;
      out_rdy  : IN     std_logic;
      out_dat  : OUT    std_logic_vector (DAT_WIDTH-1 DOWNTO 0)
   );

-- Declarations

END vr_fifo ;

--
ARCHITECTURE rtl OF vr_fifo IS
  type arymxn_type is array (2**ADR_WIDTH-1 downto 0) of std_logic_vector(DAT_WIDTH-1 downto 0);
  
  signal fifo_ary     :arymxn_type;
  signal fifo_we      :std_logic;
  signal fifo_wadr    :std_logic_vector(ADR_WIDTH-1 downto 0);
  signal fifo_re      :std_logic;
  signal fifo_radr    :std_logic_vector(ADR_WIDTH-1 downto 0);
  signal radr_dly     :std_logic_vector(ADR_WIDTH-1 downto 0):=(others=>'0');
  signal rdat         :std_logic_vector(DAT_WIDTH-1 downto 0);
  signal rdat_hld     :std_logic_vector(DAT_WIDTH-1 downto 0);
  signal re_dly       :std_logic;
  
  signal fifo_full    :std_logic;
  signal fifo_empty   :std_logic;
  
  signal vld_pn       :std_logic_vector(1 downto 0);
  
  signal in_rdy_b     :std_logic;
  signal out_vld_b    :std_logic;

  attribute block_ram : boolean; 
  attribute block_ram of fifo_ary : signal is false;

BEGIN
  
  fifo_we<=in_vld and in_rdy_b;
  fifo_re<=not fifo_empty when out_vld_b='0' else   --if there is no data in out_dat, read from FIFO
           (not fifo_empty) and out_rdy;            --if out is ready, also read
  
  proc_wr_addr:process(rst_n,clk)
  begin
    if rst_n='0' then
      fifo_wadr<=(others=>'0');
    elsif rising_edge(clk) then
      if fifo_we='1' then         --wr address adds one while every write operation
        fifo_wadr<=fifo_wadr+1;
      end if;
    end if;
  end process proc_wr_addr;
  
  proc_wr:process(clk)
  begin
    if rising_edge(clk) then
      if fifo_we='1' then         --write operation
        fifo_ary(conv_integer(fifo_wadr))<=in_dat;
      end if;
    end if;
  end process proc_wr;

  proc_fifo_rd:process(rst_n,clk)
  begin
    if rst_n='0' then
      fifo_radr<=(others=>'0');
      radr_dly<=(others=>'0');
      re_dly<='0';
    elsif rising_edge(clk) then
      if fifo_re='1' then
        fifo_radr<=fifo_radr+1;
      end if;
            
      radr_dly<=fifo_radr;    --delay
      re_dly<=fifo_re;
    end if;
  end process proc_fifo_rd;
  rdat<=fifo_ary(conv_integer(radr_dly));   --read operation
  
  proc_fifo_status:process(rst_n,clk)
  begin
    if rst_n='0' then
      fifo_full<='0';
      fifo_empty<='1';
    elsif rising_edge(clk) then
      if fifo_we='1' and fifo_re='0' and fifo_radr-fifo_wadr=1 then
        fifo_full<='1';
      elsif fifo_re='1' or fifo_empty='1' then
        fifo_full<='0';
      end if;
      
      if fifo_re='1' and fifo_we='0' and fifo_wadr-fifo_radr=1 then
        fifo_empty<='1';
      elsif fifo_we='1' then
        fifo_empty<='0';
      end if;
    end if;
  end process;
  in_rdy_b<=not fifo_full;    --it's ready for new in_dat while not full
  in_rdy<=in_rdy_b;
  
  proc_delay:process(rst_n,clk)
  begin
    if rst_n='0' then
      vld_pn<=(others=>'0');
      rdat_hld<=(others=>'0');
      out_dat<=(others=>'0');
    elsif rising_edge(clk) then
      if out_vld_b='0' or out_rdy='1' then    --trace the validity of data
        vld_pn<=vld_pn(0) & (not fifo_empty);
      end if;
      
      if re_dly='1' then          --prefetch data
        rdat_hld<=rdat;
      end if;
      
      if (out_vld_b='0' or out_rdy='1') then
        if re_dly='0' then
          out_dat<=rdat_hld;
        else
          out_dat<=rdat;
        end if;
      end if;
    end if;
  end process proc_delay;
  out_vld_b<=vld_pn(1);
  out_vld<=out_vld_b;
  
END ARCHITECTURE rtl;