polynome_pkg.vhd

可预取的fifo 的fpga 设计代码

--
-- VHDL Package Header testbench_lib.polynome
--
-- Created:
--          by - Yihua.Zhang.UNKNOWN (CV0009649D2)
--          at - 13:41:17 2006-06- 6
--
-- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

PACKAGE polynome_pkg IS
  function rev_order_f
  (
    di        :in std_logic_vector
  ) return std_logic_vector;

  ------------------------FUNCTION DESCRIPTION------------------------
  --    M sequence generator for 2^n-1
  --    xapp052
  --    ORDER = "REVERSE", shift bit from W-1 downto 0
  --    ORDER = "NORMAL", shift bit from 0 to W-1
  function mseq_f  
  (
    din       :in std_logic_vector;  --the width of din must >= n
    shift     :integer:=8;
    n         :integer:=23;
    ORDER     :string:="NORMAL";  --"REVERSE"; --    
    FEEDPOLAR :string:="INV"      --"NON-INV"
  ) return std_logic_vector;

  ------------------------FUNCTION DESCRIPTION------------------------
  --    calculation for CRC
  --    di(0), ci(0) and crc_32_f(0) is transmitted first in serial stream when REVERSE order
  --    CRC-32      :G(x)=1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
  --                :GoodFCS = 0xDEBB20E3 (REVERSE) or 0xC704DD7B(NORMAL)
  --    CRC-CCITT   :G(x)=1+x5+x12+x16
  --                :GoodFCS = 0xF0B8(REVERSE) or 0x1D0F(NORMAL)
  --    CRC-16      :G(x)=1+x2+x15+x16
  --    CRC-12      :G(x)=1+x+x2+x3+x11+x12
  --    CRC-7       :G(x)=1+x3+x7
  --    CRC-4       :G(x)=1+x+x4
  --    ORDER = "REVERSE" used for HDLC or MAC
  --    ORDER = "NORMAL" used for GFP or SDH
  function crc_f
  (
    din       :in std_logic_vector;   --direction: downto 
    cin       :in std_logic_vector;   --direction: downto 
    CRC_TYPE  :string:="CRC_32";  --"CRC_CCITT", "CRC-16", "CRC-12", "CRC_4", "CRC_7"
    BIT_ORDER :string:="NORMAL"  --"REVERSE"  --
  ) return std_logic_vector;

END polynome_pkg;