vr_fifo_tb.vhd

可预取的fifo 的fpga 设计代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

use work.polynome_pkg.all;

entity vr_fifo_tb is
end;

architecture bench of vr_fifo_tb is
component vr_fifo 
   GENERIC( 
      ADR_WIDTH : integer := 4;
      DAT_WIDTH : integer := 8
   );
   PORT( 
      rst_n    : IN     std_logic;                              
      clk      : IN     std_logic;                              
                                                                
      in_vld   : IN     std_logic;                              
      in_rdy   : OUT    std_logic;                              
      in_dat   : IN     std_logic_vector (DAT_WIDTH-1 DOWNTO 0);
                                                                
      out_vld  : OUT    std_logic;                              
      out_rdy  : IN     std_logic;                              
      out_dat  : OUT    std_logic_vector (DAT_WIDTH-1 DOWNTO 0) 
   );
end component;

  constant CLK_PRD  :time:=10 ns;
  
  signal rst_n      :std_logic;
  signal clk        :std_logic;
  signal in_vld     :std_logic;
  signal in_rdy     :std_logic;
  signal in_dat     :std_logic_vector(7 downto 0);
  signal out_vld    :std_logic;
  signal out_rdy    :std_logic;
  signal out_dat    :std_logic_vector(7 downto 0);
  
  signal rnd_dat1   :std_logic_vector(22 downto 0);
  signal rnd_dat2   :std_logic_vector(22 downto 0);
  
  signal gen_dat    :std_logic_vector(7 downto 0);
  signal chk_dat    :std_logic_vector(7 downto 0);
  signal err_ind    :std_logic;
  
  signal in_done    :std_logic;
  signal out_done   :std_logic;
begin
  proc_reset:process
  begin
    rst_n<='0';
    wait for CLK_PRD*0.6;
    rst_n<='1';
    wait;
  end process proc_reset;

  proc_clock:process
  begin
    clk<='0';
    wait for CLK_PRD/2;
    clk<='1';
    wait for CLK_PRD/2;
  end process proc_clock;

  proc_gen:process(rst_n,clk)
  begin
    if rst_n='0' then
      rnd_dat1<=(others=>'1');
      gen_dat<=(others=>'0');
    elsif rising_edge(clk) then
      if in_rdy='1' then
        rnd_dat1<=mseq_f(rnd_dat1,1,23,"NORMAL","NON-INV");
      end if;
      
      if in_done='1' then
        gen_dat<=gen_dat+1;
      end if;
    end if;
  end process proc_gen;
  in_vld<=rnd_dat1(0);
  in_dat<=gen_dat when in_vld='1' else
          (others=>'-');
  
  in_done<=in_vld and in_rdy;
  out_done<=out_vld and out_rdy;
  u_vr_fifo:vr_fifo 
   PORT map( 
      rst_n    =>rst_n,
      clk      =>clk,

      in_vld   =>in_vld,
      in_rdy   =>in_rdy,
      in_dat   =>in_dat,

      out_vld  =>out_vld,
      out_rdy  =>out_rdy,
      out_dat  =>out_dat
   );
   
  proc_out:process(rst_n,clk)
  begin
    if rst_n='0' then
      rnd_dat2<=(others=>'0');
      chk_dat<=(others=>'0');
      err_ind<='0';
    elsif rising_edge(clk) then
      if out_vld='1' then
        rnd_dat2<=mseq_f(rnd_dat2,1,23,"NORMAL","INV");      
      end if;
      
      if out_done='1' then
        chk_dat<=out_dat+1;
        if chk_dat/=out_dat then
          report("detect an error data!!!");
          err_ind<='1';
        else
          err_ind<='0';
        end if;
      end if;
    end if;
  end process proc_out;
  out_rdy<=rnd_dat2(0);

end;