polynome_pkg_body.vhd

可预取的fifo 的fpga 设计代码

--
-- VHDL Package Body testbench_lib.polynome
--
-- Created:
--          by - Yihua.Zhang.UNKNOWN (CV0009649D2)
--          at - 13:41:39 2006-06- 6
--
-- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
--
PACKAGE BODY polynome_pkg IS
  function rev_order_f
  (
    di            :in std_logic_vector
  ) return std_logic_vector is
    variable W      :integer:=di'length;        
    variable do     :std_logic_vector(di'range);
  begin
    for i in di'range loop
      do(i):=di(W -1 + di'right - i);
    end loop;
    
    return(do);
  end function rev_order_f;

  ------------------------FUNCTION DESCRIPTION------------------------
  --    M sequence generator for 2^n-1
  --    xapp052
  --    ORDER = "REVERSE", shift bit from W-1 downto 0
  --    ORDER = "NORMAL", shift bit from 0 to W-1
  function mseq_f  
  (
    din    :in std_logic_vector;  --the width of din must >= n
    shift  :integer:=8;
    n      :integer:=23;
    ORDER  :string:="NORMAL";     --"REVERSE"; --    
    FEEDPOLAR :string:="INV"      --"NON-INV"
  ) return std_logic_vector is
    constant W    :integer:=din'length;
  
    variable dt       :std_logic_vector(W+shift-1 downto 0);
    variable do       :std_logic_vector(W-1 downto 0);
    variable fb_sel   :std_logic;
  begin
    if ORDER="NORMAL" then
      dt(W+shift-1 downto shift):=din;
    elsif ORDER="REVERSE" then
      for i in W+shift-1 downto shift loop
        dt(i):=din(W+shift-1-i);
      end loop;
      else
      report("PARAMETER 'ORDER' is ERROR");      
    end if;
    
    if FEEDPOLAR="INV" then
      fb_sel:='1';
    elsif FEEDPOLAR="NON-INV" then
      fb_sel:='0';
    else
      report("PARAMETER 'FEEDPOLAR' is ERROR");
    end if;
    
    for i in shift-1 downto 0 loop
      case n is
        when 3   => dt(i):=fb_sel xor (dt(i+3) xor dt(i+2));
        when 4   => dt(i):=fb_sel xor (dt(i+4) xor dt(i+3));
        when 7   => dt(i):=fb_sel xor (dt(i+7) xor dt(i+6));
        when 9   => dt(i):=fb_sel xor (dt(i+9) xor dt(i+5));
        when 10  => dt(i):=fb_sel xor (dt(i+10) xor dt(i+7));
        when 11  => dt(i):=fb_sel xor (dt(i+11) xor dt(i+9));
        when 15  => dt(i):=fb_sel xor (dt(i+15) xor dt(i+14));
        when 19  => dt(i):=fb_sel xor (dt(i+19) xor dt(i+6) xor dt(i+2) xor dt(i+1));
        when 23  => dt(i):=fb_sel xor (dt(i+23) xor dt(i+18));
        when 33  => dt(i):=fb_sel xor (dt(i+33) xor dt(i+20));
        when 39  => dt(i):=fb_sel xor (dt(i+39) xor dt(i+35));
        when 41  => dt(i):=fb_sel xor (dt(i+41) xor dt(i+38));
        when 47  => dt(i):=fb_sel xor (dt(i+47) xor dt(i+42));
        when 63  => dt(i):=fb_sel xor (dt(i+63) xor dt(i+62));
        when 123 => dt(i):=fb_sel xor (dt(i+123) xor dt(i+121));
        when 167 => dt(i):=fb_sel xor (dt(i+167) xor dt(i+161));
        when others => dt(i):='0';
      end case;
    end loop;
    
    if ORDER="NORMAL" then
      do:=dt(W-1 downto 0);
    else
      for i in W-1 downto 0 loop
        do(i):=dt(W-1-i);
      end loop;
    end if;
  
    return (do);
  end function mseq_f;

  ------------------------FUNCTION DESCRIPTION------------------------
  --    calculation for CRC
  --    di(0), ci(0) and crc_32_f(0) is transmitted first in serial stream when REVERSE order
  --    CRC-32      :G(x)=1+x+x2+x4+x5+x7+x8+x10+x11+x12+x16+x22+x23+x26+x32
  --                :GoodFCS = 0xDEBB20E3 (REVERSE) or 0xC704DD7B(NORMAL)
  --    CRC-CCITT   :G(x)=1+x5+x12+x16
  --                :GoodFCS = 0xF0B8(REVERSE) or 0x1D0F(NORMAL)
  --    CRC-16      :G(x)=1+x2+x15+x16
  --    CRC-12      :G(x)=1+x+x2+x3+x11+x12
  --    CRC-7       :G(x)=1+x3+x7
  --    CRC-4       :G(x)=1+x+x4
  --    ORDER = "REVERSE" used for HDLC or MAC
  --    ORDER = "NORMAL" used for GFP or SDH
  function crc_f
  (
    din         :in std_logic_vector;   --direction: downto 
    cin         :in std_logic_vector;   --direction: downto 
    CRC_TYPE    :string:="CRC_32";  --"CRC_CCITT", "CRC-16", "CRC-12", "CRC_4", "CRC_7"
    BIT_ORDER   :string:="NORMAL"   --"REVERSE"  --
  ) return std_logic_vector is
    constant W    :integer:=din'length;
    
    variable ge     :std_logic_vector(31 downto 0);
    variable ct     :std_logic_vector(cin'range);
    variable fb     :std_logic;
    variable co     :std_logic_vector(cin'range);
  begin
    if CRC_TYPE="CRC_32" then
      ge(31 downto 0):="00000100110000010001110110110111";
    elsif CRC_TYPE="CRC_CCITT" then
      ge(15 downto 0):="0001000000100001";
    elsif CRC_TYPE="CRC_16" then
      ge(15 downto 0):="1000000000000101";
    elsif CRC_TYPE="CRC_12" then
      ge(11 downto 0):="100000001111";
    elsif CRC_TYPE="CRC_7" then
      ge(6 downto 0):="0001001";
    elsif CRC_TYPE="CRC_4" then
      ge(3 downto 0):="0011";
    else
      report("PARAMETER 'CRC_TYPE' is ERROR");
    end if;
      
    if BIT_ORDER="NORMAL" then
      ct:=cin;
    elsif BIT_ORDER="REVERSE" then
      ct:=rev_order_f(cin);
    else
      report("PARAMETER 'BIT_ORDER' is ERROR");
    end if;
    
    for i in W-1 downto 0 loop
      if BIT_ORDER="NORMAL" then
        fb:=ct(cin'left) xor din(i+din'right);
      elsif BIT_ORDER="REVERSE" then
        fb:=ct(cin'left) xor din(W-1-i+din'right);
      end if;
      
      for j in cin'left downto cin'right+1 loop
        ct(j):=ct(j-1) xor (fb and ge(j));
      end loop;
      ct(cin'right):= fb;
    end loop;
    
    if BIT_ORDER="NORMAL" then
      co:=ct;
    elsif BIT_ORDER="REVERSE" then
      co:=rev_order_f(ct);
    end if;
    
    return(co);
  end function crc_f;

END polynome_pkg;