generic.srd

人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习

f "noname"; #file 0
f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 1
f "c:\prj\fsm_abc\state1\state1.v"; #file 2
VNAME 'work.state1.verilog'; # view id 0
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