state2.tlg

人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习

Selecting top level module state2
@N:"C:\prj\Example-6-1\FSM\state2\state2.v":7:7:7:12|Synthesizing module state2

@N: CL201 :"C:\prj\Example-6-1\FSM\state2\state2.v":28:0:28:5|Trying to extract state machine for register CS
Extracted state machine for register CS
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   100