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人民邮电出版社<<设计与验证verilog hdl >>一书的配套光盘,包含书上所有原代码,特别是状态机部分,值得学习

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@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
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@N:  :"c:\prj\example-4-21\syn_wr\decode.v":3:7:3:12|Synthesizing module decode
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@W: BN116 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
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@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL113 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
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@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
@W: CL118 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
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@W: FO108 :"c:\prj\example-4-21\syn_wr\decode.v":17:2:17:3|M
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@N:  :"c:\prj\example-4-21\syn_wr\read_reg.v":2:7:2:14|Synthesizing module read_reg
@N:  :"c:\prj\example-4-21\syn_wr\top.v":1:7:1:9|Synthesizing module top
@N:  :"c:\prj\example-4-21\syn_wr\write_reg.v":2:7:2:15|Synthesizing module write_reg
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@W: BN116 :"c:\prj\example-4-21\syn_wr\write_reg.v":9:2:9:7|M
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@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":29:29:29:32|M
@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":30:29:30:32|M
@N: CG179 :"c:\prj\example-4-21\syn_wr\write_reg.v":31:29:31:32|M