📄 int2bit.map.rpt
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Analysis & Synthesis report for int2bit
Sat Dec 08 21:43:13 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Failed - Sat Dec 08 21:43:13 2007 ;
; Quartus II Version ; 7.1 Build 156 04/30/2007 SJ Web Edition ;
; Revision Name ; int2bit ;
; Top-level Entity Name ; int2bit ;
; Family ; FLEX10K ;
+-----------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------+-----------------+---------------+
; Device ; EPF10K20RC240-4 ; ;
; Top-level entity name ; int2bit ; int2bit ;
; Family name ; FLEX10K ; Stratix II ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Use smart compilation ; Off ; Off ;
+----------------------------------------------------------+-----------------+---------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------+------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Sat Dec 08 21:43:12 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off int2bit -c int2bit
Error (10500): VHDL syntax error at int2bit.vhd(11) near text "intnum"; expecting "(" File: F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd Line: 11
Error (10500): VHDL syntax error at int2bit.vhd(22) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement File: F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd Line: 22
Error (10500): VHDL syntax error at int2bit.vhd(23) near text "tmp_intnum"; expecting "<=" File: F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd Line: 23
Error (10500): VHDL syntax error at int2bit.vhd(25) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture" File: F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd Line: 25
Info: Found 0 design units, including 0 entities, in source file int2bit.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings
Info: Allocated 144 megabytes of memory during processing
Error: Processing ended: Sat Dec 08 21:43:13 2007
Error: Elapsed time: 00:00:01
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