prev_cmp_div_js.qmsg

技术分频器。把时钟分为奇数个

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 12 13:17:08 2008 " "Info: Processing started: Sat Jan 12 13:17:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off div_js -c div_js " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off div_js -c div_js" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "179 " "Info: Allocated 179 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 12 13:17:26 2008 " "Info: Processing ended: Sat Jan 12 13:17:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 12 13:17:28 2008 " "Info: Processing started: Sat Jan 12 13:17:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off div_js -c div_js --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div_js -c div_js --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } } { "g:/qartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/qartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register count1\[1\] tmp1 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"count1\[1\]\" and destination register \"tmp1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.807 ns + Longest register register " "Info: + Longest register to register delay is 0.807 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count1\[1\] 1 REG LCFF_X25_Y26_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y26_N7; Fanout = 4; REG Node = 'count1\[1\]'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { count1[1] } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.286 ns) + CELL(0.366 ns) 0.652 ns tmp1~33 2 COMB LCCOMB_X25_Y26_N22 1 " "Info: 2: + IC(0.286 ns) + CELL(0.366 ns) = 0.652 ns; Loc. = LCCOMB_X25_Y26_N22; Fanout = 1; COMB Node = 'tmp1~33'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { count1[1] tmp1~33 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.807 ns tmp1 3 REG LCFF_X25_Y26_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.807 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { tmp1~33 tmp1 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.521 ns ( 64.56 % ) " "Info: Total cell delay = 0.521 ns ( 64.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.286 ns ( 35.44 % ) " "Info: Total interconnect delay = 0.286 ns ( 35.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.807 ns" { count1[1] tmp1~33 tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "0.807 ns" { count1[1] tmp1~33 tmp1 } { 0.000ns 0.286ns 0.000ns } { 0.000ns 0.366ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.497 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.618 ns) 2.497 ns tmp1 3 REG LCFF_X25_Y26_N23 2 " "Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk~clkctrl tmp1 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.95 % ) " "Info: Total cell delay = 1.472 ns ( 58.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 41.05 % ) " "Info: Total interconnect delay = 1.025 ns ( 41.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl tmp1 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.497 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.618 ns) 2.497 ns count1\[1\] 3 REG LCFF_X25_Y26_N7 4 " "Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N7; Fanout = 4; REG Node = 'count1\[1\]'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk~clkctrl count1[1] } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.95 % ) " "Info: Total cell delay = 1.472 ns ( 58.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 41.05 % ) " "Info: Total interconnect delay = 1.025 ns ( 41.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl count1[1] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl count1[1] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl tmp1 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl count1[1] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl count1[1] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.807 ns" { count1[1] tmp1~33 tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "0.807 ns" { count1[1] tmp1~33 tmp1 } { 0.000ns 0.286ns 0.000ns } { 0.000ns 0.366ns 0.155ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl tmp1 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl count1[1] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl count1[1] } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { tmp1 } {  } {  } "" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clkout tmp1 5.716 ns register " "Info: tco from clock \"clk\" to destination pin \"clkout\" through register \"tmp1\" is 5.716 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.497 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.682 ns) + CELL(0.618 ns) 2.497 ns tmp1 3 REG LCFF_X25_Y26_N23 2 " "Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { clk~clkctrl tmp1 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.95 % ) " "Info: Total cell delay = 1.472 ns ( 58.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.025 ns ( 41.05 % ) " "Info: Total interconnect delay = 1.025 ns ( 41.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl tmp1 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.125 ns + Longest register pin " "Info: + Longest register to pin delay is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp1 1 REG LCFF_X25_Y26_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp1 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.346 ns) 0.610 ns clkout~0 2 COMB LCCOMB_X25_Y26_N30 1 " "Info: 2: + IC(0.264 ns) + CELL(0.346 ns) = 0.610 ns; Loc. = LCCOMB_X25_Y26_N30; Fanout = 1; COMB Node = 'clkout~0'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.610 ns" { tmp1 clkout~0 } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.479 ns) + CELL(2.036 ns) 3.125 ns clkout 3 PIN PIN_D10 0 " "Info: 3: + IC(0.479 ns) + CELL(2.036 ns) = 3.125 ns; Loc. = PIN_D10; Fanout = 0; PIN Node = 'clkout'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.515 ns" { clkout~0 clkout } "NODE_NAME" } } { "div_js.vhd" "" { Text "F:/school/EDA/王志娟EDA/div_js/div_js.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.382 ns ( 76.22 % ) " "Info: Total cell delay = 2.382 ns ( 76.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.743 ns ( 23.78 % ) " "Info: Total interconnect delay = 0.743 ns ( 23.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { tmp1 clkout~0 clkout } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { tmp1 clkout~0 clkout } { 0.000ns 0.264ns 0.479ns } { 0.000ns 0.346ns 2.036ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.497 ns" { clk clk~clkctrl tmp1 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.497 ns" { clk clk~combout clk~clkctrl tmp1 } { 0.000ns 0.000ns 0.343ns 0.682ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.125 ns" { tmp1 clkout~0 clkout } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "3.125 ns" { tmp1 clkout~0 clkout } { 0.000ns 0.264ns 0.479ns } { 0.000ns 0.346ns 2.036ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 12 13:17:29 2008 " "Info: Processing ended: Sat Jan 12 13:17:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 6 s " "Info: Quartus II Full Compilation was successful. 0 errors, 6 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}