votema.vhd

来自「投票器。这个好像是3人投票器」· VHDL 代码 · 共 21 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY VoteMa IS
PORT(a,b,c:IN STD_LOGIC;
	aa,bb,cc:OUT STD_LOGIC;
	d:OUT STD_LOGIC);
END ENTITY VoteMa;

ARCHITECTURE dataflow OF VoteMa IS
SIGNAL tmp1,tmp2,tmp3:STD_LOGIC;
BEGIN
tmp1<=a AND b;
tmp2<=a AND c;
tmp3<=c AND b;
d<=tmp1 OR (tmp2 OR tmp3);
aa<=a;
bb<=b;
cc<=c;
END ARCHITECTURE dataflow;