📄 clkdiv_2p5.tan.rpt
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Classic Timing Analyzer report for ClkDiv_2p5
Mon Dec 03 11:48:53 2007
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
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to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 17.600 ns ; tmpdiv2p5 ; clkdiv2p5 ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[1] ; counter[0] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+------------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K20RC240-4 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[0] ; tmpdiv2p5 ; clk ; clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[0] ; counter[1] ; clk ; clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[1] ; counter[0] ; clk ; clk ; None ; None ; 2.300 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[1] ; tmpdiv2p5 ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[1] ; counter[1] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; counter[0] ; counter[0] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 125.00 MHz ( period = 8.000 ns ) ; clkdiv5 ; clkdiv5 ; clk ; clk ; None ; None ; 1.800 ns ;
+-------+------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------+-----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------+-----------+------------+
; N/A ; None ; 17.600 ns ; tmpdiv2p5 ; clkdiv2p5 ; clk ;
+-------+--------------+------------+-----------+-----------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
Info: Processing started: Mon Dec 03 11:48:52 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ClkDiv_2p5 -c ClkDiv_2p5
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clkdiv5" as buffer
Info: Detected gated clock "tmpclk" as buffer
Info: Detected ripple clock "tmpdiv2p5" as buffer
Info: Clock "clk" Internal fmax is restricted to 125.0 MHz between source register "counter[0]" and destination register "tmpdiv2p5"
Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.300 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F2; Fanout = 3; REG Node = 'counter[0]'
Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'
Info: Total cell delay = 1.700 ns ( 73.91 % )
Info: Total interconnect delay = 0.600 ns ( 26.09 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 10.500 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'
Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'
Info: Total cell delay = 4.600 ns ( 43.81 % )
Info: Total interconnect delay = 5.900 ns ( 56.19 % )
Info: - Longest clock path from clock "clk" to source register is 10.500 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'
Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC3_F2; Fanout = 3; REG Node = 'counter[0]'
Info: Total cell delay = 4.600 ns ( 43.81 % )
Info: Total interconnect delay = 5.900 ns ( 56.19 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Info: tco from clock "clk" to destination pin "clkdiv2p5" through register "tmpdiv2p5" is 17.600 ns
Info: + Longest clock path from clock "clk" to source register is 10.500 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'
Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'
Info: Total cell delay = 4.600 ns ( 43.81 % )
Info: Total interconnect delay = 5.900 ns ( 56.19 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 6.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'
Info: 2: + IC(0.900 ns) + CELL(5.100 ns) = 6.000 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'clkdiv2p5'
Info: Total cell delay = 5.100 ns ( 85.00 % )
Info: Total interconnect delay = 0.900 ns ( 15.00 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Allocated 106 megabytes of memory during processing
Info: Processing ended: Mon Dec 03 11:48:54 2007
Info: Elapsed time: 00:00:02
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