clock.map.qmsg

这是一个实现时分秒的时钟功能的源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 20 11:02:17 2008 " "Info: Processing started: Thu Mar 20 11:02:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clock -c clock " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter10-Behavioral " "Info: Found design unit 1: counter10-Behavioral" {  } { { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter10 " "Info: Found entity 1: counter10" {  } { { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter6.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter6.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter6-Behavioral " "Info: Found design unit 1: counter6-Behavioral" {  } { { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter6 " "Info: Found entity 1: counter6" {  } { { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-Behavioral " "Info: Found design unit 1: counter24-Behavioral" {  } { { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-Behavioral " "Info: Found design unit 1: decoder-Behavioral" {  } { { "decoder.vhd" "" { Text "F:/mywork/clock/decoder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "F:/mywork/clock/decoder.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-Behavioral " "Info: Found design unit 1: clock-Behavioral" {  } { { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "F:/mywork/clock/clock.bdf " "Warning: Can't analyze file -- file F:/mywork/clock/clock.bdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "clock " "Info: Elaborating entity \"clock\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter10 counter10:u1 " "Info: Elaborating entity \"counter10\" for hierarchy \"counter10:u1\"" {  } { { "clock.vhd" "u1" { Text "F:/mywork/clock/clock.vhd" 58 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter6 counter6:u2 " "Info: Elaborating entity \"counter6\" for hierarchy \"counter6:u2\"" {  } { { "clock.vhd" "u2" { Text "F:/mywork/clock/clock.vhd" 62 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter24 counter24:u5 " "Info: Elaborating entity \"counter24\" for hierarchy \"counter24:u5\"" {  } { { "clock.vhd" "u5" { Text "F:/mywork/clock/clock.vhd" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:u6 " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:u6\"" {  } { { "clock.vhd" "u6" { Text "F:/mywork/clock/clock.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "hourl\[5\] GND " "Warning: Pin \"hourl\[5\]\" stuck at GND" {  } { { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "138 " "Info: Implemented 138 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "22 " "Info: Implemented 22 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "74 " "Info: Implemented 74 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 20 11:02:21 2008 " "Info: Processing ended: Thu Mar 20 11:02:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}