clock.tan.qmsg

这是一个实现时分秒的时钟功能的源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 6 -1 0 } } { "d:/quartus2/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter6:u4\|c " "Info: Detected ripple clock \"counter6:u4\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } } { "d:/quartus2/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "counter6:u4\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u3\|c " "Info: Detected ripple clock \"counter10:u3\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } } { "d:/quartus2/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "counter10:u3\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter6:u2\|c " "Info: Detected ripple clock \"counter6:u2\|c\" as buffer" {  } { { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } } { "d:/quartus2/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "counter6:u2\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u1\|c " "Info: Detected ripple clock \"counter10:u1\|c\" as buffer" {  } { { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } } { "d:/quartus2/bin/Assignment Editor.qase" "" { Assignment "d:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "counter10:u1\|c" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register counter24:u5\|count\[0\] counter24:u5\|count\[3\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"counter24:u5\|count\[0\]\" and destination register \"counter24:u5\|count\[3\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.375 ns + Longest register register " "Info: + Longest register to register delay is 3.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[0\] 1 REG LC_X9_Y13_N3 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N3; Fanout = 13; REG Node = 'counter24:u5\|count\[0\]'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "" { counter24:u5|count[0] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.852 ns) + CELL(0.292 ns) 1.144 ns rtl~131 2 COMB LC_X10_Y13_N2 2 " "Info: 2: + IC(0.852 ns) + CELL(0.292 ns) = 1.144 ns; Loc. = LC_X10_Y13_N2; Fanout = 2; COMB Node = 'rtl~131'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "1.144 ns" { counter24:u5|count[0] rtl~131 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.445 ns) + CELL(0.590 ns) 2.179 ns counter24:u5\|count~242 3 COMB LC_X10_Y13_N1 3 " "Info: 3: + IC(0.445 ns) + CELL(0.590 ns) = 2.179 ns; Loc. = LC_X10_Y13_N1; Fanout = 3; COMB Node = 'counter24:u5\|count~242'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "1.035 ns" { rtl~131 counter24:u5|count~242 } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.458 ns) + CELL(0.738 ns) 3.375 ns counter24:u5\|count\[3\] 4 REG LC_X10_Y13_N8 11 " "Info: 4: + IC(0.458 ns) + CELL(0.738 ns) = 3.375 ns; Loc. = LC_X10_Y13_N8; Fanout = 11; REG Node = 'counter24:u5\|count\[3\]'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "1.196 ns" { counter24:u5|count~242 counter24:u5|count[3] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.620 ns ( 48.00 % ) " "Info: Total cell delay = 1.620 ns ( 48.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.755 ns ( 52.00 % ) " "Info: Total interconnect delay = 1.755 ns ( 52.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "3.375 ns" { counter24:u5|count[0] rtl~131 counter24:u5|count~242 counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "3.375 ns" { counter24:u5|count[0] rtl~131 counter24:u5|count~242 counter24:u5|count[3] } { 0.000ns 0.852ns 0.445ns 0.458ns } { 0.000ns 0.292ns 0.590ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 24.456 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 24.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns counter10:u1\|c 2 REG LC_X6_Y8_N6 4 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X6_Y8_N6; Fanout = 4; REG Node = 'counter10:u1\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "1.658 ns" { clk counter10:u1|c } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.380 ns) + CELL(0.935 ns) 8.442 ns counter6:u2\|c 3 REG LC_X31_Y18_N8 5 " "Info: 3: + IC(4.380 ns) + CELL(0.935 ns) = 8.442 ns; Loc. = LC_X31_Y18_N8; Fanout = 5; REG Node = 'counter6:u2\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.315 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } "" } } { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.790 ns) + CELL(0.935 ns) 14.167 ns counter10:u3\|c 4 REG LC_X22_Y11_N7 4 " "Info: 4: + IC(4.790 ns) + CELL(0.935 ns) = 14.167 ns; Loc. = LC_X22_Y11_N7; Fanout = 4; REG Node = 'counter10:u3\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.725 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.588 ns) + CELL(0.935 ns) 19.690 ns counter6:u4\|c 5 REG LC_X28_Y9_N4 6 " "Info: 5: + IC(4.588 ns) + CELL(0.935 ns) = 19.690 ns; Loc. = LC_X28_Y9_N4; Fanout = 6; REG Node = 'counter6:u4\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.523 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } "" } } { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.055 ns) + CELL(0.711 ns) 24.456 ns counter24:u5\|count\[3\] 6 REG LC_X10_Y13_N8 11 " "Info: 6: + IC(4.055 ns) + CELL(0.711 ns) = 24.456 ns; Loc. = LC_X10_Y13_N8; Fanout = 11; REG Node = 'counter24:u5\|count\[3\]'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "4.766 ns" { counter6:u4|c counter24:u5|count[3] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 24.21 % ) " "Info: Total cell delay = 5.920 ns ( 24.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.536 ns ( 75.79 % ) " "Info: Total interconnect delay = 18.536 ns ( 75.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 24.456 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 24.456 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 5 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "" { clk } "NODE_NAME" } "" } } { "clock.vhd" "" { Text "F:/mywork/clock/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.935 ns) 3.127 ns counter10:u1\|c 2 REG LC_X6_Y8_N6 4 " "Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X6_Y8_N6; Fanout = 4; REG Node = 'counter10:u1\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "1.658 ns" { clk counter10:u1|c } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.380 ns) + CELL(0.935 ns) 8.442 ns counter6:u2\|c 3 REG LC_X31_Y18_N8 5 " "Info: 3: + IC(4.380 ns) + CELL(0.935 ns) = 8.442 ns; Loc. = LC_X31_Y18_N8; Fanout = 5; REG Node = 'counter6:u2\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.315 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } "" } } { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.790 ns) + CELL(0.935 ns) 14.167 ns counter10:u3\|c 4 REG LC_X22_Y11_N7 4 " "Info: 4: + IC(4.790 ns) + CELL(0.935 ns) = 14.167 ns; Loc. = LC_X22_Y11_N7; Fanout = 4; REG Node = 'counter10:u3\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.725 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } "" } } { "counter10.vhd" "" { Text "F:/mywork/clock/counter10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.588 ns) + CELL(0.935 ns) 19.690 ns counter6:u4\|c 5 REG LC_X28_Y9_N4 6 " "Info: 5: + IC(4.588 ns) + CELL(0.935 ns) = 19.690 ns; Loc. = LC_X28_Y9_N4; Fanout = 6; REG Node = 'counter6:u4\|c'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "5.523 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } "" } } { "counter6.vhd" "" { Text "F:/mywork/clock/counter6.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.055 ns) + CELL(0.711 ns) 24.456 ns counter24:u5\|count\[0\] 6 REG LC_X9_Y13_N3 13 " "Info: 6: + IC(4.055 ns) + CELL(0.711 ns) = 24.456 ns; Loc. = LC_X9_Y13_N3; Fanout = 13; REG Node = 'counter24:u5\|count\[0\]'" {  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "4.766 ns" { counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.920 ns ( 24.21 % ) " "Info: Total cell delay = 5.920 ns ( 24.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.536 ns ( 75.79 % ) " "Info: Total interconnect delay = 18.536 ns ( 75.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "3.375 ns" { counter24:u5|count[0] rtl~131 counter24:u5|count~242 counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "3.375 ns" { counter24:u5|count[0] rtl~131 counter24:u5|count~242 counter24:u5|count[3] } { 0.000ns 0.852ns 0.445ns 0.458ns } { 0.000ns 0.292ns 0.590ns 0.738ns } } } { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[3] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } } { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "24.456 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "24.456 ns" { clk clk~out0 counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[0] } { 0.000ns 0.000ns 0.723ns 4.380ns 4.790ns 4.588ns 4.055ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "" { counter24:u5|count[3] } "NODE_NAME" } "" } } { "d:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/bin/Technology_Viewer.qrui" "" { counter24:u5|count[3] } {  } {  } } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}