📄 clock.fit.qmsg
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{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 4 40 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 4 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 45 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 45 pins available" { } { } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!d! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0} } { } 0 0 "Statistics of %1!s!" 0 0} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.542 ns register register " "Info: Estimated most critical path is register to register delay of 2.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[0\] 1 REG LAB_X9_Y13 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y13; Fanout = 13; REG Node = 'counter24:u5\|count\[0\]'" { } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "" { counter24:u5|count[0] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.376 ns) + CELL(0.590 ns) 0.966 ns rtl~131 2 COMB LAB_X10_Y13 2 " "Info: 2: + IC(0.376 ns) + CELL(0.590 ns) = 0.966 ns; Loc. = LAB_X10_Y13; Fanout = 2; COMB Node = 'rtl~131'" { } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "0.966 ns" { counter24:u5|count[0] rtl~131 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.372 ns) + CELL(0.292 ns) 1.630 ns rtl~4 3 COMB LAB_X10_Y13 1 " "Info: 3: + IC(0.372 ns) + CELL(0.292 ns) = 1.630 ns; Loc. = LAB_X10_Y13; Fanout = 1; COMB Node = 'rtl~4'" { } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "0.664 ns" { rtl~131 rtl~4 } "NODE_NAME" } "" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.309 ns) 2.542 ns counter24:u5\|count\[5\] 4 REG LAB_X10_Y13 5 " "Info: 4: + IC(0.603 ns) + CELL(0.309 ns) = 2.542 ns; Loc. = LAB_X10_Y13; Fanout = 5; REG Node = 'counter24:u5\|count\[5\]'" { } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "0.912 ns" { rtl~4 counter24:u5|count[5] } "NODE_NAME" } "" } } { "counter24.vhd" "" { Text "F:/mywork/clock/counter24.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.191 ns ( 46.85 % ) " "Info: Total cell delay = 1.191 ns ( 46.85 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.351 ns ( 53.15 % ) " "Info: Total interconnect delay = 1.351 ns ( 53.15 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/quartus2/bin/Report_Window_01.qrpt" "" { Report "d:/quartus2/bin/Report_Window_01.qrpt" "Compiler" "clock" "UNKNOWN" "V1" "F:/mywork/clock/db/clock.quartus_db" { Floorplan "F:/mywork/clock/" "" "2.542 ns" { counter24:u5|count[0] rtl~131 rtl~4 counter24:u5|count[5] } "NODE_NAME" } "" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
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