clock.tan.rpt

这是一个实现时分秒的时钟功能的源码

; N/A   ; None         ; 19.646 ns  ; counter10:u3|count[1] ; minutel[2] ; clk        ;
; N/A   ; None         ; 19.526 ns  ; counter10:u3|count[1] ; minutel[4] ; clk        ;
; N/A   ; None         ; 19.436 ns  ; counter10:u3|count[0] ; minutel[0] ; clk        ;
; N/A   ; None         ; 19.432 ns  ; counter10:u3|count[0] ; minutel[2] ; clk        ;
; N/A   ; None         ; 19.346 ns  ; counter10:u3|count[3] ; minutel[2] ; clk        ;
; N/A   ; None         ; 19.342 ns  ; counter10:u3|count[3] ; minutel[0] ; clk        ;
; N/A   ; None         ; 19.325 ns  ; counter10:u3|count[0] ; minutel[4] ; clk        ;
; N/A   ; None         ; 19.247 ns  ; counter10:u3|count[3] ; minutel[4] ; clk        ;
; N/A   ; None         ; 13.642 ns  ; counter6:u2|count[1]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 13.533 ns  ; counter6:u2|count[0]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 13.444 ns  ; counter6:u2|count[0]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 13.330 ns  ; counter6:u2|count[2]  ; secondh[6] ; clk        ;
; N/A   ; None         ; 13.315 ns  ; counter6:u2|count[0]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 13.304 ns  ; counter6:u2|count[0]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 13.277 ns  ; counter6:u2|count[1]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 13.185 ns  ; counter6:u2|count[2]  ; secondh[1] ; clk        ;
; N/A   ; None         ; 13.141 ns  ; counter6:u2|count[1]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 13.134 ns  ; counter6:u2|count[1]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 13.079 ns  ; counter6:u2|count[0]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 13.068 ns  ; counter6:u2|count[0]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 13.050 ns  ; counter6:u2|count[2]  ; secondh[3] ; clk        ;
; N/A   ; None         ; 13.034 ns  ; counter6:u2|count[2]  ; secondh[4] ; clk        ;
; N/A   ; None         ; 12.997 ns  ; counter6:u2|count[0]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 12.898 ns  ; counter6:u2|count[1]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 12.892 ns  ; counter6:u2|count[1]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 12.815 ns  ; counter6:u2|count[1]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 12.799 ns  ; counter6:u2|count[2]  ; secondh[2] ; clk        ;
; N/A   ; None         ; 12.798 ns  ; counter6:u2|count[2]  ; secondh[0] ; clk        ;
; N/A   ; None         ; 12.716 ns  ; counter6:u2|count[2]  ; secondh[5] ; clk        ;
; N/A   ; None         ; 8.884 ns   ; counter10:u1|count[3] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.848 ns   ; counter10:u1|count[3] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.565 ns   ; counter10:u1|count[3] ; secondl[2] ; clk        ;
; N/A   ; None         ; 8.553 ns   ; counter10:u1|count[3] ; secondl[1] ; clk        ;
; N/A   ; None         ; 8.465 ns   ; counter10:u1|count[0] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.460 ns   ; counter10:u1|count[0] ; secondl[5] ; clk        ;
; N/A   ; None         ; 8.437 ns   ; counter10:u1|count[3] ; secondl[3] ; clk        ;
; N/A   ; None         ; 8.429 ns   ; counter10:u1|count[0] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.343 ns   ; counter10:u1|count[1] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.312 ns   ; counter10:u1|count[1] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.281 ns   ; counter10:u1|count[0] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.279 ns   ; counter10:u1|count[1] ; secondl[5] ; clk        ;
; N/A   ; None         ; 8.177 ns   ; counter10:u1|count[3] ; secondl[5] ; clk        ;
; N/A   ; None         ; 8.145 ns   ; counter10:u1|count[0] ; secondl[2] ; clk        ;
; N/A   ; None         ; 8.141 ns   ; counter10:u1|count[2] ; secondl[4] ; clk        ;
; N/A   ; None         ; 8.138 ns   ; counter10:u1|count[0] ; secondl[1] ; clk        ;
; N/A   ; None         ; 8.115 ns   ; counter10:u1|count[2] ; secondl[0] ; clk        ;
; N/A   ; None         ; 8.100 ns   ; counter10:u1|count[1] ; secondl[6] ; clk        ;
; N/A   ; None         ; 8.026 ns   ; counter10:u1|count[1] ; secondl[1] ; clk        ;
; N/A   ; None         ; 8.024 ns   ; counter10:u1|count[1] ; secondl[2] ; clk        ;
; N/A   ; None         ; 8.017 ns   ; counter10:u1|count[0] ; secondl[3] ; clk        ;
; N/A   ; None         ; 7.998 ns   ; counter10:u1|count[3] ; secondl[6] ; clk        ;
; N/A   ; None         ; 7.969 ns   ; counter10:u1|count[2] ; secondl[5] ; clk        ;
; N/A   ; None         ; 7.895 ns   ; counter10:u1|count[1] ; secondl[3] ; clk        ;
; N/A   ; None         ; 7.828 ns   ; counter10:u1|count[2] ; secondl[1] ; clk        ;
; N/A   ; None         ; 7.822 ns   ; counter10:u1|count[2] ; secondl[2] ; clk        ;
; N/A   ; None         ; 7.787 ns   ; counter10:u1|count[2] ; secondl[6] ; clk        ;
; N/A   ; None         ; 7.693 ns   ; counter10:u1|count[2] ; secondl[3] ; clk        ;
+-------+--------------+------------+-----------------------+------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Mar 20 11:02:46 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter6:u4|c" as buffer
    Info: Detected ripple clock "counter10:u3|c" as buffer
    Info: Detected ripple clock "counter6:u2|c" as buffer
    Info: Detected ripple clock "counter10:u1|c" as buffer
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "counter24:u5|count[0]" and destination register "counter24:u5|count[3]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.375 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N3; Fanout = 13; REG Node = 'counter24:u5|count[0]'
            Info: 2: + IC(0.852 ns) + CELL(0.292 ns) = 1.144 ns; Loc. = LC_X10_Y13_N2; Fanout = 2; COMB Node = 'rtl~131'
            Info: 3: + IC(0.445 ns) + CELL(0.590 ns) = 2.179 ns; Loc. = LC_X10_Y13_N1; Fanout = 3; COMB Node = 'counter24:u5|count~242'
            Info: 4: + IC(0.458 ns) + CELL(0.738 ns) = 3.375 ns; Loc. = LC_X10_Y13_N8; Fanout = 11; REG Node = 'counter24:u5|count[3]'
            Info: Total cell delay = 1.620 ns ( 48.00 % )
            Info: Total interconnect delay = 1.755 ns ( 52.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 24.456 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X6_Y8_N6; Fanout = 4; REG Node = 'counter10:u1|c'
                Info: 3: + IC(4.380 ns) + CELL(0.935 ns) = 8.442 ns; Loc. = LC_X31_Y18_N8; Fanout = 5; REG Node = 'counter6:u2|c'
                Info: 4: + IC(4.790 ns) + CELL(0.935 ns) = 14.167 ns; Loc. = LC_X22_Y11_N7; Fanout = 4; REG Node = 'counter10:u3|c'
                Info: 5: + IC(4.588 ns) + CELL(0.935 ns) = 19.690 ns; Loc. = LC_X28_Y9_N4; Fanout = 6; REG Node = 'counter6:u4|c'
                Info: 6: + IC(4.055 ns) + CELL(0.711 ns) = 24.456 ns; Loc. = LC_X10_Y13_N8; Fanout = 11; REG Node = 'counter24:u5|count[3]'
                Info: Total cell delay = 5.920 ns ( 24.21 % )
                Info: Total interconnect delay = 18.536 ns ( 75.79 % )
            Info: - Longest clock path from clock "clk" to source register is 24.456 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X6_Y8_N6; Fanout = 4; REG Node = 'counter10:u1|c'
                Info: 3: + IC(4.380 ns) + CELL(0.935 ns) = 8.442 ns; Loc. = LC_X31_Y18_N8; Fanout = 5; REG Node = 'counter6:u2|c'
                Info: 4: + IC(4.790 ns) + CELL(0.935 ns) = 14.167 ns; Loc. = LC_X22_Y11_N7; Fanout = 4; REG Node = 'counter10:u3|c'
                Info: 5: + IC(4.588 ns) + CELL(0.935 ns) = 19.690 ns; Loc. = LC_X28_Y9_N4; Fanout = 6; REG Node = 'counter6:u4|c'
                Info: 6: + IC(4.055 ns) + CELL(0.711 ns) = 24.456 ns; Loc. = LC_X9_Y13_N3; Fanout = 13; REG Node = 'counter24:u5|count[0]'
                Info: Total cell delay = 5.920 ns ( 24.21 % )
                Info: Total interconnect delay = 18.536 ns ( 75.79 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "hourl[6]" through register "counter24:u5|count[5]" is 31.911 ns
    Info: + Longest clock path from clock "clk" to source register is 24.456 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(0.723 ns) + CELL(0.935 ns) = 3.127 ns; Loc. = LC_X6_Y8_N6; Fanout = 4; REG Node = 'counter10:u1|c'
        Info: 3: + IC(4.380 ns) + CELL(0.935 ns) = 8.442 ns; Loc. = LC_X31_Y18_N8; Fanout = 5; REG Node = 'counter6:u2|c'
        Info: 4: + IC(4.790 ns) + CELL(0.935 ns) = 14.167 ns; Loc. = LC_X22_Y11_N7; Fanout = 4; REG Node = 'counter10:u3|c'
        Info: 5: + IC(4.588 ns) + CELL(0.935 ns) = 19.690 ns; Loc. = LC_X28_Y9_N4; Fanout = 6; REG Node = 'counter6:u4|c'
        Info: 6: + IC(4.055 ns) + CELL(0.711 ns) = 24.456 ns; Loc. = LC_X10_Y13_N4; Fanout = 5; REG Node = 'counter24:u5|count[5]'
        Info: Total cell delay = 5.920 ns ( 24.21 % )
        Info: Total interconnect delay = 18.536 ns ( 75.79 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.231 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y13_N4; Fanout = 5; REG Node = 'counter24:u5|count[5]'
        Info: 2: + IC(3.582 ns) + CELL(0.292 ns) = 3.874 ns; Loc. = LC_X24_Y1_N2; Fanout = 2; COMB Node = 'decoder:u11|dout[6]~73'
        Info: 3: + IC(1.249 ns) + CELL(2.108 ns) = 7.231 ns; Loc. = PIN_101; Fanout = 0; PIN Node = 'hourl[6]'
        Info: Total cell delay = 2.400 ns ( 33.19 % )
        Info: Total interconnect delay = 4.831 ns ( 66.81 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Mar 20 11:02:46 2008
    Info: Elapsed time: 00:00:02